Multi-Level Network-on-Chip Design Based on Embedded Unified Rendering GPU

2022 ◽  
pp. 1313-1320
Author(s):  
Ye Li ◽  
Huiming Du ◽  
Libo Chang ◽  
Haowen Wang
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Multi Level ◽  
On Chip

scholarly journals DIA-TORUS:A Novel Topology for Network on Chip Design

2016 ◽  
Vol 8 (3) ◽  
pp. 137-148
Author(s):  
Deewakar Thakyal ◽  
Pushpita Chatterjee
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
On Chip

scholarly journals Network-on-Chip design and synthesis outlook

Integration ◽  
2008 ◽  
Vol 41 (3) ◽  
pp. 340-359 ◽  
Author(s):  
David Atienza ◽  
Federico Angiolini ◽  
Srinivasan Murali ◽  
Antonio Pullini ◽  
Luca Benini ◽  
...  
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Design And Synthesis ◽  
On Chip

On-Chip Processor Traffic Modeling for Network-on-Chip Design

2009 ◽  
pp. 95-121
Author(s):  
Antoine Scherrer ◽  
Tanguy Risset ◽  
Antoine Fraboulet
Keyword(s):  
Network On Chip ◽  
Traffic Modeling ◽  
Chip Design ◽  
On Chip

scholarly journals Timing-Error-Tolerant Network-on-Chip Design Methodology

2007 ◽  
Vol 26 (7) ◽  
pp. 1297-1310 ◽  
Author(s):  
Rutuparna Tamhankar ◽  
Srinivasan Murali ◽  
Stergios Stergiou ◽  
Antonio Pullini ◽  
Federico Angiolini ◽  
...  
Keyword(s):  
Design Methodology ◽  
Network On Chip ◽  
Timing Error ◽  
Chip Design ◽  
On Chip

Photonic Network-on-Chip Design

2014 ◽  
Author(s):  
Keren Bergman ◽  
Luca P. Carloni ◽  
Aleksandr Biberman ◽  
Johnnie Chan ◽  
Gilbert Hendry
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Photonic Network ◽  
On Chip

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

2019 ◽  
pp. 442-454
Author(s):  
P. Veda Bhanu ◽  
Pranav V. Kulkarni ◽  
Sai Pranavi Avadhanam ◽  
J. Soumya ◽  
Linga Reddy Cenkeramaddi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Reconfigurable Architecture ◽  
Chip Design ◽  
Mesh Topology ◽  
On Chip
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