Introduction to Logic Circuits & Logic Design with VHDL

Author(s):  
Brock J. LaMeres
Keyword(s):  
2020 ◽  
Vol 30 (15) ◽  
pp. 2050222
Author(s):  
Li Luo ◽  
Zhekang Dong ◽  
Xiaofang Hu ◽  
Lidan Wang ◽  
Shukai Duan

The nanoscale implementations of ternary logic circuits are particularly attractive because of high information density and operation speed that can be achieved by using emerging memristor technologies. Memristor is a nanoscale device with nonvolatility and adjustable multilevel states, which creates an intriguing opportunity for the implementation of ternary logic operations. This paper proposes a novel memristor-based design for stateful ternary logic, including AND, OR, NOT, NAND, NOR, and COPY operations. In the proposed memristor ternary logic (MTL) design, the resistance of memristor is the only logic state variable for representing the input and output. By sensing the value of the input memristors, the resistance of the output memristor changes accordingly. Furthermore, the MTL gates are not only capable of performing logic operations, but also storing logic values. To illustrate the potential of the methodology, a single-input-three-output ternary decoder is designed by using the proposed ternary logic circuits. Simulation results verify the effectiveness of the presented design.


2005 ◽  
Vol 14 (03) ◽  
pp. 507-513 ◽  
Author(s):  
DONG-HAHK LEE

This letter presents a new architecture for othogonal variable spreading factor (OVSF) code generator. The basic idea of the proposed method is to generate the code sequence using the outputs of binary counter and the binary representation of the code number. The proposed architecture can generate the code sequences as adding the only combinational logic circuits without an additional counter, if other code sequences are required according to SFs. Since the proposed generator is applied to W-CDMA modem that used different SFs simultaneously, it contributes to the reduction of the modem hardware complexity.


2020 ◽  
Vol 29 (10) ◽  
pp. 2050164
Author(s):  
C. Pavlatos ◽  
A. C. Dimopoulos ◽  
G. Papakonstantinou

Using logic gates is the traditional way of designing logic circuits. However, in many cases, the use of modules is advantageous as the module is considered a uniform structure composed of multiple gates. In this paper, a nonlinear approach is proposed for designing logic circuits for use as modules multiplexers (MUXs) or Reed–Muller universal blocks (RMs). The experimental results show that the method gives better results compared to other methods available in the literature. The main advantages of the method are that it guarantees minimality and it can also handle Boolean functions for incompletely specified functions. The method is general enough and can be used for any kind of modules.


2006 ◽  
Vol 15 (02) ◽  
pp. 277-287 ◽  
Author(s):  
KO YOSHIKAWA ◽  
SHIGETO INUI ◽  
YASUHIKO HAGIHARA ◽  
YUICHI NAKAMURA ◽  
TAKESHI YOSHIMURA

We have developed a domino logic synthesis system with a new technology mapping algorithm based on a bin packing algorithm that reduces the levels of the circuits and considers the complexity of domino primitive cells. Domino logic circuits have 20–50% performance advantage over static circuits. By using this system, designing domino logic circuits becomes much easier than manual design. The primary reason is that logic design is completely automated by the system. The second reason is that domino primitive cell layout is simplified by our new technology mapping algorithms that considers the complexity of domino primitive cells.


Author(s):  
Guy Even ◽  
Moti Medina
Keyword(s):  

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