MTL: Memristor Ternary Logic Design

2020 ◽  
Vol 30 (15) ◽  
pp. 2050222
Author(s):  
Li Luo ◽  
Zhekang Dong ◽  
Xiaofang Hu ◽  
Lidan Wang ◽  
Shukai Duan
Keyword(s):  
Logic Circuits ◽  
Logic Design ◽  
Ternary Logic ◽  
Nanoscale Device ◽  
State Variable ◽  
Operation Speed ◽  
Input And Output ◽  
Single Input ◽  
Logic Operations ◽  
High Information

The nanoscale implementations of ternary logic circuits are particularly attractive because of high information density and operation speed that can be achieved by using emerging memristor technologies. Memristor is a nanoscale device with nonvolatility and adjustable multilevel states, which creates an intriguing opportunity for the implementation of ternary logic operations. This paper proposes a novel memristor-based design for stateful ternary logic, including AND, OR, NOT, NAND, NOR, and COPY operations. In the proposed memristor ternary logic (MTL) design, the resistance of memristor is the only logic state variable for representing the input and output. By sensing the value of the input memristors, the resistance of the output memristor changes accordingly. Furthermore, the MTL gates are not only capable of performing logic operations, but also storing logic values. To illustrate the potential of the methodology, a single-input-three-output ternary decoder is designed by using the proposed ternary logic circuits. Simulation results verify the effectiveness of the presented design.

Novel Approach to Design DPL-based Ternary Logic Circuits

2018 ◽  
Author(s):  
Narendra Deo Singh ◽  
Rakesh Kumar Singh ◽  
Rahul Raj ◽  
Shivam Jyoti ◽  
Aloke Saha
Keyword(s):  
Logic Circuits ◽  
Ternary Logic ◽  
Novel Approach

scholarly journals A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 385
Author(s):  
Qiao Wang ◽  
Donglin Zhang ◽  
Yulin Zhao ◽  
Chao Liu ◽  
Qiao Hu ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Reliability ◽  
Charge Sharing ◽  
Operation Speed ◽  
Sharing Function ◽  
Logic Operations ◽  
A Charge ◽  
Process Compatibility ◽  
Ferroelectric Capacitors

Ferroelectric capacitors (FeCAPs) with high process compatibility, high reliability, ultra-low programming current and fast operation speed are promising candidates to traditional volatile and nonvolatile memory. In addition, they have great potential in the fields of storage, computing, and memory logic. Nevertheless, effective methods to realize logic and memory in FeCAP devices are still lacking. This study proposes a 1T2C FeCAP-based in situ bitwise X(N)OR logic based on a charge-sharing function. First, using the 1T2C structure and a two-step write-back circuit, the nondestructive reading is realized with less complexity than the previous work. Second, a method of two-line activation is used during the operation of X(N)OR. The verification results show that the speed, area and power consumption of the proposed 1T2C FeCAP-based bitwise logic operations are significantly improved.

ON THE HYBRID-DRIVEN LINKAGE MECHANISM WITH ONE INPUT CYCLE CORRESPONDING TO TWO OUTPUT CYCLES

2015 ◽  
Vol 39 (3) ◽  
pp. 637-646
Author(s):  
Ren-Chung Soong
Keyword(s):  
Kinematic Analysis ◽  
Angular Speed ◽  
Motion Trajectory ◽  
Dimensional Synthesis ◽  
Reciprocating Motion ◽  
Linkage Mechanism ◽  
Output Link ◽  
Input And Output ◽  
Single Input ◽  
Selection Of

A hybrid-driven five-bar linkage mechanism with one input cycle corresponding to two output cycles is presented. The proposed linkage mechanism is driven by a constant-speed motor and a linear motor, respectively. The output link can generate two same required output cycles during a single input cycle, while the rotational input link rotates with a constant angular speed, and the linear input link follows a reciprocating motion along a specified linear guide fixed on the rotational input link. The configuration, displacement relationship between the input and output links, and conditions of mobility of this proposed mechanism were studied, and a kinematic analysis was performed. The selection of the instantaneous motion trajectory of the linear input link and an optimal dimensional synthesis are also described. An example is provided to verify the feasibility and effectiveness of this methodology.

PROCEDURES FOR LOGIC AND ARITHMETIC OPERATIONS WITH DNA MOLECULES

2004 ◽  
Vol 15 (03) ◽  
pp. 461-474 ◽  
Author(s):  
AKIHIRO FUJIWARA ◽  
KEN'ICHI MATSUMOTO ◽  
WEI CHEN
Keyword(s):  
Truth Table ◽  
Boolean Operation ◽  
Dna Molecules ◽  
Boolean Operations ◽  
Arithmetic Operations ◽  
Input And Output ◽  
Dna Strands ◽  
Logic Operations ◽  
N Additions

In this paper, we consider procedures for logic and arithmetic operations with DNA molecules. We first show a DNA representation of n binary numbers of m bits, and propose a procedure to assign the same values for the representation. The representation enables addressing feature, and the procedure is applicable to n binary numbers of m bits in O(1) steps in parallel. Next, we propose a procedure for logic operations. The procedure enables any boolean operation whose input and output are defined by a truth table, and executes different kinds of boolean operations simultaneously for any pair of n binary numbers of m bits in O(1) lab steps using O(mn) DNA strands. Finally, we propose a procedure for additions of pairs of two binary numbers. The procedure executes O(n) additions of two m-bit binary numbers in O(1) steps using O(mn) DNA strands.

Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High‐Performance, Low‐Power Flexible Ternary Logic Circuits

Small ◽  
2021 ◽  
pp. 2103365
Author(s):  
Chungryeol Lee ◽  
Junhwan Choi ◽  
Hongkeun Park ◽  
Changhyeon Lee ◽  
Chang‐Hyun Kim ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Logic Circuits ◽  
Ternary Logic ◽  
Systematic Control ◽  
Heterojunction Transistor

scholarly journals Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 542 ◽  
Author(s):  
Haifeng Zhang ◽  
Zhaowei Zhang ◽  
Mingyu Gao ◽  
Li Luo ◽  
Shukai Duan ◽  
...  
Keyword(s):  
High Efficiency ◽  
Load Capacity ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Ternary Logic ◽  
Logic Operations ◽  
Almost All ◽  
Logic Functions

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.

Sign in / Sign up

Export Citation Format

Share Document