Influence of Software Optimization on Energy Consumption of Embedded Systems

Author(s):  
Alexander Chemeris ◽  
Dmitri Lazorenko ◽  
Sergey Sushko
2008 ◽  
Vol 43 (7) ◽  
pp. 23-30 ◽  
Author(s):  
Carmen Badea ◽  
Alexandru Nicolau ◽  
Alexander V. Veidenbaum

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Chen Guo ◽  
Song Ci ◽  
Yanglin Zhou ◽  
Yang Yang

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Lhassane Idoumghar ◽  
Mahmoud Melkemi ◽  
René Schott ◽  
Maha Idrissi Aouad

The paper presents a novel hybrid evolutionary algorithm that combines Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms. When a local optimal solution is reached with PSO, all particles gather around it, and escaping from this local optima becomes difficult. To avoid premature convergence of PSO, we present a new hybrid evolutionary algorithm, called HPSO-SA, based on the idea that PSO ensures fast convergence, while SA brings the search out of local optima because of its strong local-search ability. The proposed HPSO-SA algorithm is validated on ten standard benchmark multimodal functions for which we obtained significant improvements. The results are compared with these obtained by existing hybrid PSO-SA algorithms. In this paper, we provide also two versions of HPSO-SA (sequential and distributed) for minimizing the energy consumption in embedded systems memories. The two versions, of HPSO-SA, reduce the energy consumption in memories from 76% up to 98% as compared to Tabu Search (TS). Moreover, the distributed version of HPSO-SA provides execution time saving of about 73% up to 84% on a cluster of 4 PCs.


2009 ◽  
Vol 18 (01) ◽  
pp. 181-198 ◽  
Author(s):  
XIAO XIN XIA ◽  
TENG TIOW TAY

Energy consumption is one of the most important design constraints for modern microprocessors, and designers have proposed many energy-saving techniques. Looking beyond the traditional hardware low-power designs, software optimization is becoming a significant strategy for the microprocessor to lower its energy consumption. This paper describes an intra-application identification and reconfiguration mechanism for microprocessor energy reduction. Our mechanism employs a statistical sampling method during training runs to identify code sections among application that have appropriate IPC (Instructions per Cycle) values and could make contributions to program runtime energy reduction, and then profiles them to dynamically scale the voltage and frequency of the microprocessor at appropriate points during execution. In our simulation, our approach achieves energy savings by an average of 39% with minor performance degradation, compared to a processor running at a fixed voltage and speed.


Author(s):  
José Antonio Esparza Isasa ◽  
Peter Würtz Vinther Jørgensen ◽  
Claus Ballegård Nielsen ◽  
Stefan Hallerstede

2008 ◽  
Vol 57 (4) ◽  
pp. 797-804 ◽  
Author(s):  
V. Konstantakos ◽  
A. Chatzigeorgiou ◽  
S. Nikolaidis ◽  
T. Laopoulos

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