Static Syntax Validation for Code Generation with String Templates

SDL 2017: Model-Driven Engineering for Future Internet - Lecture Notes in Computer Science ◽

10.1007/978-3-319-68015-6_2 ◽

2017 ◽

pp. 18-29

Author(s):

Dorian Weber ◽

Joachim Fischer

Keyword(s):

Code Generation

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ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e98.a.2494 ◽

2015 ◽

Vol E98.A (12) ◽

pp. 2494-2504 ◽

Cited By ~ 2

Author(s):

Masashi TAWADA ◽

Shinji KIMURA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

Code Generation ◽

Non Volatile Memory ◽

Volatile Memory

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Privacy Concern Code Generation Using Crypto Neural Scheme

International Journal of Computer Sciences and Engineering ◽

10.26438/ijcse/v7i5.824828 ◽

2019 ◽

Vol 7 (5) ◽

pp. 824-828

Author(s):

Anaswara Venunadh ◽

Shruthi N ◽

Mannar Mannan

Keyword(s):

Code Generation ◽

Privacy Concern

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Real-time C Code Generation in Ptolemy II for the Giotto Model of Computation

10.21236/ada538394 ◽

2009 ◽

Author(s):

Shanna-Shaye Forbes

Keyword(s):

Real Time ◽

Code Generation ◽

Model Of Computation

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Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization

10.1145/3368826 ◽

2020 ◽

Keyword(s):

International Symposium ◽

Code Generation ◽

Ieee International Symposium

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Realization of NAND FLASH Control Glueless Interface Circuit

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.1008-1009.659 ◽

2014 ◽

Vol 1008-1009 ◽

pp. 659-662

Author(s):

Hai Ke Liu ◽

Shun Wang ◽

Xin Gna Kang ◽

Jin Liang Wang

Keyword(s):

Error Correction ◽

Code Generation ◽

Nand Flash ◽

Timing Control ◽

Interface Circuit ◽

Advantages And Disadvantages ◽

Operation Sequence ◽

Control Interface

The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.

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