Realization of NAND FLASH Control Glueless Interface Circuit

2014 ◽  
Vol 1008-1009 ◽  
pp. 659-662
Author(s):  
Hai Ke Liu ◽  
Shun Wang ◽  
Xin Gna Kang ◽  
Jin Liang Wang
Keyword(s):  
Error Correction ◽  
Code Generation ◽  
Nand Flash ◽  
Timing Control ◽  
Interface Circuit ◽  
Advantages And Disadvantages ◽  
Operation Sequence ◽  
Control Interface

The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

METHODS FOR ENSURING THE STABILITY OF THE ELECTRONIC COMPONENT BASE TO SINGLE EVENTS BY REDUNDANCY

2021 ◽  
Vol 14 (1) ◽  
pp. 10-16
Author(s):  
Aleksandr Kozyukov ◽  
Vladimir Zolnikov ◽  
Svetlana Evdokimova ◽  
Oleg Kvasov ◽  
Konstantin Yakovlev ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Electronic Component ◽  
Hamming Code ◽  
Program Code ◽  
Advantages And Disadvantages ◽  
Irregular Structures ◽  
Residual Code ◽  
The Stability

The article discusses algorithmic methods for ensuring the fault tolerance of the electronic component base (ECB). The protection methods used in regular and irregular structures are described. The essence of Hamming code algorithms, composite code, error correction and detection codes is revealed. The advantages and disadvantages of using arithmetic residual code, the method of redundancy at the level of program code fragments, are shown.

Introduction of FECs and its Applications on Internet & Wireless Communications

2011 ◽  
Vol 403-408 ◽  
pp. 1776-1780
Author(s):  
Yan Ma ◽  
Chun Lan Ma
Keyword(s):  
Wireless Communications ◽  
Error Correction ◽  
Error Correction Coding ◽  
Advantages And Disadvantages ◽  
Coding Method ◽  
Different Types

This article focuses on FECs which is an error correction coding method and its applications in Internet and wireless communications. First, this article begins with the principles and the types of FECs. Then some typical applications n Internet and Wireless communications for each type of FECs are outlined. The next step is a comparison of the advantages and disadvantages between different types of FECs.

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

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