scholarly journals Software Cannot Protect Software: An Argument for Dedicated Hardware in Security and a Categorization of the Trustworthiness of Information

2008 ◽  
pp. 36-48
Author(s):  
Matthew Judge ◽  
Paul Williams ◽  
Yong Kim ◽  
Barry Mullins
Keyword(s):  
Dedicated Hardware

Integrated Heterogeneous Micro-Nano Systems via Modular Designing and Flexible Assembly

2011 ◽  
Author(s):  
Aditya Das ◽  
Rakesh Murthy
Keyword(s):  
Uncertainty Propagation ◽  
Systems Development ◽  
Surface Machining ◽  
Flexible Assembly ◽  
Nano Scale ◽  
Wide Range ◽  
Standard Design ◽  
Novel Algorithms ◽  
And Control ◽  
Dedicated Hardware

One of the major challenges in commercializable micro-nano systems development is the high cost and turnaround that are incurred through multiple product-optimization iterations and expensive fabrication processes for specific systems. Development of complex and heterogeneous micro-nano systems, that are only possible through assembly and not by conventional surface machining approaches, are further impeded by lack of standard design rules and off-the-shelf robotic manipulation systems. Dedicated hardware and system specific component designs, although possible, are not commercially viable for addressing the wide range of opportunities that exists in the prevailing micro-nano domain. In this paper, we present an alternative and holistic top-down approach for micro-nano manufacturing using modular part designs and flexible assembly systems. We incorporate, seamlessly, multiple novel algorithms related to microrobotics and scaling of physics, obtained both analytically as well as experimentally; in order to predict, track and control the uncertainty propagation in a typical manufacturing process, in micro-nano scale, throughout production steps including design, machining, setup, assembly, testing etc. We demonstrate, through multiple examples, the implementation of the proposed framework in micro-nano scale manufacturing.

Dedicated hardware implementation of a high precision power quality meter

2015 ◽  
Author(s):  
Victor Valente de Araujo ◽  
Raul Acosta Hernandez ◽  
Eduardo Simas ◽  
Amauri Oliveira ◽  
Wagner L. A. de Olivera
Keyword(s):  
Power Quality ◽  
High Precision ◽  
Hardware Implementation ◽  
Dedicated Hardware

scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

Data Handling and Dedicated Hardware for the Sort Problem

1983 ◽  
pp. 205-226 ◽  
Author(s):  
W. Teich ◽  
H. Ch. Zeidler
Keyword(s):  
Data Handling ◽  
Dedicated Hardware

A Promising Hardware Accelerator with PAST Adder

2021 ◽  
Vol 105 ◽  
pp. 241-248
Author(s):  
Abhishek Choubey ◽  
Shruti Bhargava Choubey
Keyword(s):  
Neural Network ◽  
Machine Learning ◽  
Resource Utilization ◽  
Network Inference ◽  
Hardware Accelerator ◽  
High Complexity ◽  
High Resource ◽  
The Neural Network ◽  
And Storage ◽  
Dedicated Hardware

Recent neural network research has demonstrated a significant benefit in machine learning compared to conventional algorithms based on handcrafted models and features. In regions such as video, speech and image recognition, the neural network is now widely adopted. But the high complexity of neural network inference in computation and storage poses great differences on its application. These networks are computer-intensive algorithms that currently require the execution of dedicated hardware. In this case, we point out the difficulty of Adders (MOAs) and their high-resource utilization in a CNN implementation of FPGA .to address these challenge a parallel self-time adder is implemented which mainly aims at minimizing the amount of transistors and estimating different factors for PASTA, i.e. field, power, delay.

Elliptic Curve Cryptography on WISPs

2013 ◽  
pp. 562-583
Author(s):  
Michael Hutter ◽  
Erich Wenger ◽  
Markus Pelnar ◽  
Christian Pendl
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Public Key ◽  
Wireless Sensor ◽  
Binary Field ◽  
Montgomery Ladder ◽  
Sensing Platforms ◽  
Cryptographic Primitive ◽  
Prime Fields ◽  
Dedicated Hardware

In this chapter, the authors explore the feasibility of Elliptic Curve Cryptography (ECC) on Wireless Identification and Sensing Platforms (WISPs). ECC is a public-key based cryptographic primitive that has been widely adopted in embedded systems and Wireless Sensor Networks (WSNs). In order to demonstrate the practicability of ECC on such platforms, the authors make use of the passively powered WISP4.1DL UHF tag from Intel Research Seattle. They implemented ECC over 192-bit prime fields and over 191-bit binary extension fields and performed a Montgomery ladder scalar multiplication on WISPs with and without a dedicated hardware multiplier. The investigations show that when running at a frequency of 6.7 MHz, WISP tags that do not support a hardware multiplier need 8.3 seconds and only 1.6 seconds when a hardware multiplier is supported. The binary-field implementation needs about 2 seconds without support of a hardware multiplier. For the WISP, ECC over prime fields provides best performance when a hardware multiplier is available; binary-field based implementations are recommended otherwise. The use of ECC on WISPs allows the realization of different public-key based protocols in order to provide various cryptographic services such as confidentiality, data integrity, non-repudiation, and authentication.

Elliptic Curve Cryptography on WISPs

2013 ◽  
pp. 120-143
Author(s):  
Michael Hutter ◽  
Erich Wenger ◽  
Markus Pelnar ◽  
Christian Pendl
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Public Key ◽  
Wireless Sensor ◽  
Binary Field ◽  
Montgomery Ladder ◽  
Sensing Platforms ◽  
Cryptographic Primitive ◽  
Prime Fields ◽  
Dedicated Hardware

In this chapter, the authors explore the feasibility of Elliptic Curve Cryptography (ECC) on Wireless Identification and Sensing Platforms (WISPs). ECC is a public-key based cryptographic primitive that has been widely adopted in embedded systems and Wireless Sensor Networks (WSNs). In order to demonstrate the practicability of ECC on such platforms, the authors make use of the passively powered WISP4.1DL UHF tag from Intel Research Seattle. They implemented ECC over 192-bit prime fields and over 191-bit binary extension fields and performed a Montgomery ladder scalar multiplication on WISPs with and without a dedicated hardware multiplier. The investigations show that when running at a frequency of 6.7 MHz, WISP tags that do not support a hardware multiplier need 8.3 seconds and only 1.6 seconds when a hardware multiplier is supported. The binary-field implementation needs about 2 seconds without support of a hardware multiplier. For the WISP, ECC over prime fields provides best performance when a hardware multiplier is available; binary-field based implementations are recommended otherwise. The use of ECC on WISPs allows the realization of different public-key based protocols in order to provide various cryptographic services such as confidentiality, data integrity, non-repudiation, and authentication.

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