scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

scholarly journals A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm Using Verilog HDL

2021 ◽  
Vol 9 (VII) ◽  
pp. 1876-1879
Author(s):  
Charrith Srinivaas
Keyword(s):  
Advanced Encryption Standard ◽  
Verilog Hdl ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Rapid Pace ◽  
Tools And Techniques ◽  
Day By Day

As the technology is getting more and more advanced day by day in a rapid pace the problem for the security of data is also increasing at a very staggering rate. The hackers are equipped with new advanced tools and techniques to break any security system. Hence people are getting even more concerned about their data and data’s security. The data security can be achieved by either software or hardware implementations or both put together working in harmony. In this work Field Programmable Gate Arrays (FPGA) device is used for hardware implementation since these devices are less complex, more flexible and provide and have far greater more efficiency. This work mainly focuses on the hardware execution of one of the security algorithms that is the Advanced Encryption Standard (AES) algorithm which is the most highly used algorithm for Encryption. The AES algorithm is executed on Vivado 2014.2 ISE Design Suite and therefore the results are observed on 28 nanometers (nm) Artix-7 FPGA. This work Mainly discusses the design implementation of the AES algorithm and the resources which are consumed in implementing the AES design on Artix-7 FPGA. The resources which are consumed are as follows- Slice Register (SR), Look-Up Tables (LUTs), Input/Output (I/O) and Global Buffer.

scholarly journals High-Level Synthesis: Productivity, Performance, and Software Constraints

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Yun Liang ◽  
Kyle Rupnow ◽  
Yinan Li ◽  
Dongbo Min ◽  
Minh N. Do ◽  
...  
Keyword(s):  
Stereo Matching ◽  
Feature Matching ◽  
General Purpose ◽  
High Level Synthesis ◽  
Future Directions ◽  
Hardware Implementations ◽  
Rtl Design ◽  
Order Of Magnitude ◽  
High Level

FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high—often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4X to 126X speedup over the software version. The stereo matching algorithms achieve between 3.5X and 67.9X speedup over software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.

scholarly journals High Level Synthesis Optimizations of Road Lane Detection Development on Zynq-7000

2021 ◽  
Vol 29 (2) ◽  
Author(s):  
Panadda Solod ◽  
Nattha Jindapetch ◽  
Kiattisak Sengchuai ◽  
Apidet Booranawong ◽  
Pakpoom Hoyingcharoen ◽  
...  
Keyword(s):  
Low Cost ◽  
Optimization Techniques ◽  
Lane Detection ◽  
High Level Synthesis ◽  
Resource Usage ◽  
Clock Frequency ◽  
Loop Analysis ◽  
Loop Unrolling ◽  
Loop Pipelining ◽  
High Level

In this work, we proposed High-Level Synthesis (HLS) optimization processes to improve the speed and the resource usage of complex algorithms, especially nested-loop. The proposed HLS optimization processes are divided into four steps: array sizing is performed to decrease the resource usage on Programmable Logic (PL) part, loop analysis is performed to determine which loop must be loop unrolling or loop pipelining, array partitioning is performed to resolve the bottleneck of loop unrolling and loop pipelining, and HLS interface is performed to select the best block level and port level interface for array argument of RTL design. A case study road lane detection was analyzed and applied with suitable optimization techniques to implement on the Xilinx Zynq-7000 family (Zybo ZC7010-1) which was a low-cost FPGA. From the experimental results, our proposed method reaches 6.66 times faster than the primitive method at clock frequency 100 MHz or about 6 FPS. Although the proposed methods cannot reach the standard real-time (25 FPS), they can instruct HLS developers for speed increasing and resource decreasing on an FPGA.

scholarly journals Implementation of Advanced Encryption Standard (AES) and QR Code Algorithm on Digital Legalization System

2018 ◽  
Vol 73 ◽  
pp. 13009
Author(s):  
Okfalisa ◽  
Novi Yanti ◽  
Wahyu Aidil Dita Surya ◽  
Amany Akhyar ◽  
A Ambarwati Frica
Keyword(s):  
Memory Load ◽  
Black Box ◽  
Advanced Encryption Standard ◽  
Qr Code ◽  
Aes Algorithm ◽  
Code Algorithm ◽  
Black Box Testing ◽  
High Level ◽  
Response Testing ◽  
Server System

A certificate is an important document that its validity must be ascertained. Fraud over the originality of this document demands a high level of security to ensure that this document is genuine. The Digital Certificate Legalization system (DCL) can regulate and guarantee the mechanism of document validity procedure. By implementing AES and QR Code algorithm, the information contained in the photo-scan of the certificate can be authenticated. The results of the scan are encrypted by using the legalized code in AES Algorithm. The code will be translated using the QR Code and matched to the data contained in the server system. The system will confirm whether the certificate is original or not. In order to test the system, black box testing is applied for functionality check; capacity testing in terms of execution time and memory load of benchmark testing are also examined for system performance measurement. Finally, user response testing is conducted to identify the user acceptance towards the system. As the result, the implementation of AES and QR Code algorithm provides good performance, efficient, light, and fast execution responses (less than one second and less than one megabyte) in a legalized certification checking system.

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