Adaptive Fault Tolerance for Many-Core Based Space-Borne Computing

2010 ◽  
pp. 260-274
Author(s):  
Mark James ◽  
Paul Springer ◽  
Hans Zima
Keyword(s):  
Fault Tolerance ◽  
Many Core

Fault-Tolerance at the Management Level in Many-Core Systems

2018 ◽  
Author(s):  
Vinicius Fochi ◽  
Luciano L. Caimi ◽  
Marcelo H. da Silva ◽  
Fernando Gehm Moraes
Keyword(s):  
Fault Tolerance ◽  
Management Level ◽  
Many Core

scholarly journals Software-based fault tolerance for the Maestro many-core processor

2011 ◽  
Author(s):  
John Paul Walters ◽  
Robert Kost ◽  
Karandeep Singh ◽  
Jinwoo Suh ◽  
Stephen P. Crago
Keyword(s):  
Fault Tolerance ◽  
Many Core

Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems

2013 ◽  
Vol 29 (2) ◽  
pp. 159-175 ◽  
Author(s):  
Cristiana Bolchini ◽  
Matteo Carminati ◽  
Antonio Miele
Keyword(s):  
Fault Tolerance ◽  
Many Core ◽  
Self Adaptive

scholarly journals Power-Aware Fault-Tolerance for Embedded Systems

2020 ◽  
pp. 565-588
Author(s):  
Mohammad Salehi ◽  
Florian Kriebel ◽  
Semeen Rehman ◽  
Muhammad Shafique
Keyword(s):  
Fault Tolerance ◽  
Performance Management ◽  
Performance Level ◽  
System Level ◽  
Dark Silicon ◽  
Silicon Chips ◽  
Power Reliability ◽  
And Performance ◽  
Reliability Performance ◽  
Many Core

AbstractPower-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (RMT). In dark silicon chips, the maximum number of cores that can simultaneously be powered-on (at the full performance level) is constrained by the thermal design power (TDP). The rest of the cores have to be power-gated (i.e., stay “dark”), or the cores have to operate at a lower performance level. It has been predicted that about 25–50% of a many-core chip can potentially be “dark.” In this chapter, a system-level power–reliability management technique is presented. The technique jointly considers multiple hardening modes at the software and hardware levels, each offering distinct power, reliability, and performance properties. Also, a framework for the system-level optimization is introduced which considers different power–reliability–performance management problems for many-core processors depending upon the target system and user constraints.

scholarly journals NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

2018 ◽  
Vol 8 (3) ◽  
pp. 465 ◽  
Author(s):  
Vanessa Vargas ◽  
Pablo Ramos ◽  
Jean-Francois Méhaut ◽  
Raoul Velazco
Keyword(s):  
Fault Tolerance ◽  
Tolerance Approach ◽  
Many Core
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