Cost Effective High-Voltage IC Technology Implemented in a Standard CMOS Process

Author(s):  
Jong Mun Park ◽  
Rainer Minixhofer ◽  
Martin Schrems
2013 ◽  
Vol 446-447 ◽  
pp. 901-906 ◽  
Author(s):  
Wei Qi Gao ◽  
Hui Wan ◽  
Jin Zhang ◽  
Pin Yang ◽  
Yan Lin Zhang ◽  
...  

A 16-bit multi-channel simultaneous sampling ADC of wide analog input was designed. This ADC had a maximum conversion rate of 250[kSPS]. The ADC was implemented in 0.6[um] 2P3M standard CMOS process+high voltage CMOS process. For ±10 [V]/10[kHz] sine analog input and 250[kSPS] sampling rate, the testing result of the ADC at room temperature is that INL is 1.7[LSB], SINAD is 85.3[dB], EFS-is 0.055[%FS], EFS+ is 0.039[%FS].


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