Proceedings of International Electron Devices Meeting
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236

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23

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0780327004

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EEPROM/flash sub 3.0 V drain-source bias hot carrier writing

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499382 ◽

2002 ◽

Author(s):

J.D. Bude ◽

A. Frommer ◽

M.R. Pinto ◽

G.R. Weber

Keyword(s):

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Ta/sub 2/O/sub 5/ capacitors' dielectric material for giga-bit DRAMs

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.497194 ◽

2002 ◽

Author(s):

Y. Ohji ◽

Y. Matsui ◽

T. Itoga ◽

M. Hirayama ◽

Y. Sugawara ◽

...

Keyword(s):

Dielectric Material

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Reducing operating voltage from 3, 2, to 1 volt and below-challenges and guidelines for possible solutions [CMOS]

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.497181 ◽

2002 ◽

Author(s):

Ran-Hong Yan ◽

D. Monroe ◽

J. Weis ◽

A. Mujtaba ◽

E. Westerwick

Keyword(s):

Operating Voltage

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Thermal analysis of vertically integrated circuits

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499244 ◽

2002 ◽

Author(s):

M.B. Kleiner ◽

S.A. Kuhn ◽

P. Ramm ◽

W. Weber

Keyword(s):

Thermal Analysis ◽

Integrated Circuits

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Modeling arsenic activation and diffusion during furnace and rapid thermal annealing

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.497187 ◽

2002 ◽

Author(s):

E. Vandenbossche ◽

H. Jaouen ◽

B. Baccus

Keyword(s):

Thermal Annealing ◽

Rapid Thermal Annealing ◽

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A PN gate polysilicon thin film transistor

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499346 ◽

2002 ◽

Author(s):

Byung-Hyuk Min ◽

Cheol-Min Park ◽

Min-Koo Han

Keyword(s):

Thin Film ◽

Thin Film Transistor

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A novel 0.25 μm CMOS technology for 6.82 μm/sup 2/ 6-Tr. SRAM cell with elevated trench isolation and line-and-space shaped gates (ETILS)

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499388 ◽

2002 ◽

Author(s):

T. Nakabayashi ◽

T. Uehara ◽

M. Segawa ◽

T. Ukeda ◽

M. Yamanaka ◽

...

Keyword(s):

Cmos Technology ◽

Sram Cell ◽

Trench Isolation

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In-situ Ga/sub 2/O/sub 3/ process for GaAs inversion/accumulation device and surface passivation applications

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499220 ◽

2002 ◽

Author(s):

M. Passlack ◽

Minghwei Hong ◽

J.P. Mannaerts ◽

S.N.G. Chu ◽

R.L. Opila ◽

...

Keyword(s):

Surface Passivation

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A scalable low power vertical memory

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499305 ◽

2002 ◽

Author(s):

H.I. Hanafi ◽

S. Tiwari ◽

S. Burns ◽

W. Kocon ◽

A. Thomas ◽

...

Keyword(s):

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Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499323 ◽

2002 ◽

Author(s):

M. Ugajin ◽

J. Kodate ◽

Y. Kobayashi ◽

S. Konaka ◽

T. Sakai

Keyword(s):

High Performance ◽

Bipolar Transistors ◽

Process Technology ◽

Ultra High Speed ◽

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