Proceedings of International Electron Devices Meeting
Latest Publications

TOTAL DOCUMENTS

236

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780327004

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499323 ◽

2002 ◽

Cited By ~ 7

Author(s):

M. Ugajin ◽

J. Kodate ◽

Y. Kobayashi ◽

S. Konaka ◽

T. Sakai

Keyword(s):

High Speed ◽

High Performance ◽

Bipolar Transistors ◽

Low Energy ◽

Process Technology ◽

Ultra High Speed ◽

Very High

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Impact of surface proximity gettering and nitrided oxide side-wall spacer by nitrogen implantation on sub-quarter micron CMOS LDD FETs

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499352 ◽

2002 ◽

Cited By ~ 1

Author(s):

S. Shimizu ◽

T. Kuroi ◽

Y. Kawasaki ◽

S. Kusunoki ◽

Y. Okumura ◽

...

Keyword(s):

Side Wall ◽

Nitrogen Implantation ◽

Surface Proximity

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Reversal of temperature dependence of integrated circuits operating at very low voltages

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.497185 ◽

2002 ◽

Cited By ~ 33

Author(s):

Changhae Park ◽

J.P. John ◽

K. Klein ◽

J. Teplik ◽

J. Caravella ◽

...

Keyword(s):

Integrated Circuits ◽

Temperature Dependence

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Thermal analysis of vertically integrated circuits

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499244 ◽

2002 ◽

Cited By ~ 32

Author(s):

M.B. Kleiner ◽

S.A. Kuhn ◽

P. Ramm ◽

W. Weber

Keyword(s):

Thermal Analysis ◽

Integrated Circuits

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Modeling arsenic activation and diffusion during furnace and rapid thermal annealing

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.497187 ◽

2002 ◽

Cited By ~ 1

Author(s):

E. Vandenbossche ◽

H. Jaouen ◽

B. Baccus

Keyword(s):

Thermal Annealing ◽

Rapid Thermal Annealing ◽

And Diffusion

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A PN gate polysilicon thin film transistor

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499346 ◽

2002 ◽

Author(s):

Byung-Hyuk Min ◽

Cheol-Min Park ◽

Min-Koo Han

Keyword(s):

Thin Film ◽

Thin Film Transistor

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A novel 0.25 μm CMOS technology for 6.82 μm/sup 2/ 6-Tr. SRAM cell with elevated trench isolation and line-and-space shaped gates (ETILS)

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499388 ◽

2002 ◽

Author(s):

T. Nakabayashi ◽

T. Uehara ◽

M. Segawa ◽

T. Ukeda ◽

M. Yamanaka ◽

...

Keyword(s):

Cmos Technology ◽

Sram Cell ◽

Trench Isolation

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In-situ Ga/sub 2/O/sub 3/ process for GaAs inversion/accumulation device and surface passivation applications

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499220 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Passlack ◽

Minghwei Hong ◽

J.P. Mannaerts ◽

S.N.G. Chu ◽

R.L. Opila ◽

...

Keyword(s):

Surface Passivation

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A scalable low power vertical memory

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499305 ◽

2002 ◽

Cited By ~ 5

Author(s):

H.I. Hanafi ◽

S. Tiwari ◽

S. Burns ◽

W. Kocon ◽

A. Thomas ◽

...

Keyword(s):

Low Power

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EEPROM/flash sub 3.0 V drain-source bias hot carrier writing

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499382 ◽

2002 ◽

Cited By ~ 30

Author(s):

J.D. Bude ◽

A. Frommer ◽

M.R. Pinto ◽

G.R. Weber

Keyword(s):

Hot Carrier

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Proceedings of International Electron Devices MeetingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Impact of surface proximity gettering and nitrided oxide side-wall spacer by nitrogen implantation on sub-quarter micron CMOS LDD FETs

Reversal of temperature dependence of integrated circuits operating at very low voltages

Thermal analysis of vertically integrated circuits

Modeling arsenic activation and diffusion during furnace and rapid thermal annealing

A PN gate polysilicon thin film transistor

A novel 0.25 μm CMOS technology for 6.82 μm/sup 2/ 6-Tr. SRAM cell with elevated trench isolation and line-and-space shaped gates (ETILS)

In-situ Ga/sub 2/O/sub 3/ process for GaAs inversion/accumulation device and surface passivation applications

A scalable low power vertical memory

EEPROM/flash sub 3.0 V drain-source bias hot carrier writing

Proceedings of International Electron Devices Meeting
Latest Publications