Cache Efficiency and Scalability on Multi-core Architectures

Memory Mapping and Parallelizing Random Forests for Speed and Cache Efficiency

10.1145/3458744.3474052 ◽

2021 ◽

Author(s):

Eduardo Romero-Gainza ◽

Christopher Stewart ◽

Angela Li ◽

Kyle Hale ◽

Nathaniel Morris

Keyword(s):

Random Forests ◽

Memory Mapping ◽

Cache Efficiency

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Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection

Proceedings of the 47th International Conference on Parallel Processing - ICPP 2018 ◽

10.1145/3225058.3225104 ◽

2018 ◽

Cited By ~ 1

Author(s):

Xian Zhu ◽

Robert Wernsman ◽

Joseph Zambreno

Keyword(s):

Cache Efficiency

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IMPROVING peLIFO CACHE REPLACEMENT POLICY: HARDWARE REDUCTION AND THREAD-AWARE EXTENSION

Journal of Circuits System and Computers ◽

10.1142/s0218126614500467 ◽

2014 ◽

Vol 23 (04) ◽

pp. 1450046

Author(s):

ENRIQUE SEDANO ◽

SILVIO SEPULVEDA ◽

FERNANDO CASTRO ◽

DANIEL CHAVER ◽

RODRIGO GONZALEZ-ALBERQUILLA ◽

...

Keyword(s):

New York ◽

Replacement Policy ◽

Cache Replacement ◽

Dynamic Information ◽

Processor Performance ◽

Replacement Algorithm ◽

L2 Cache ◽

Cache Efficiency ◽

Performance Penalty

Studying blocks behavior during their lifetime in cache can provide useful information to reduce the miss rate and therefore improve processor performance. According to this rationale, the peLIFO replacement algorithm [M. Chaudhuri, Proc. Micro'09, New York, 12–16 December, 2009, pp. 401–412], which learns dynamically the number of cache ways required to satisfy short-term reuses preserving the remaining ways for long-term reuses, has been recently proposed. In this paper, we propose several changes to the original peLIFO policy in order to reduce the implementation complexity involved, and we extend the algorithm to a shared-cache environment considering dynamic information about threads behavior to improve cache efficiency. Experimental results confirm that our simplification techniques reduce the required hardware with a negligible performance penalty, while the best of our thread-aware extension proposals reduces average CPI by 8.7% and 15.2% on average compared to the original peLIFO and LRU respectively for a set of 43 multi-programmed workloads on an 8 MB 16-way set associative shared L2 cache.

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