On a Class of Exponentiated Adaptive Algorithms for the Identification of Sparse Impulse Responses

For a spatial audio reproduction in the context of augmented reality, a position-dynamic binaural synthesis system can be used to synthesize the ear signals for a moving listener. The goal is the fusion of the auditory perception of the virtual audio objects with the real listening environment. Such a system has several components, each of which help to enable a plausible auditory simulation. For each possible position of the listener in the room, a set of binaural room impulse responses (BRIRs) congruent with the expected auditory environment is required to avoid room divergence effects. Adequate and efficient approaches are methods to synthesize new BRIRs using very few measurements of the listening room. The required spatial resolution of the BRIR positions can be estimated by spatial auditory perception thresholds. Retrieving and processing the tracking data of the listener’s head-pose and position as well as convolving BRIRs with an audio signal needs to be done in real-time. This contribution presents work done by the authors including several technical components of such a system in detail. It shows how the single components are affected by psychoacoustics. Furthermore, the paper also discusses the perceptive effect by means of listening tests demonstrating the appropriateness of the approaches.

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Feedback cancellation in digital hearing aids using convex combination of proportionate adaptive algorithms

Applied Acoustics ◽

10.1016/j.apacoust.2021.108175 ◽

2021 ◽

Vol 182 ◽

pp. 108175

Author(s):

Ravi Vanamadi ◽

Asutosh Kar

Keyword(s):

Hearing Aids ◽

Convex Combination ◽

Adaptive Algorithms ◽

Feedback Cancellation ◽

Digital Hearing Aids

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Decision Tree-Based Adaptive Reconfigurable Cache Scheme

Algorithms ◽

10.3390/a14060176 ◽

2021 ◽

Vol 14 (6) ◽

pp. 176

Author(s):

Wei Zhu ◽

Xiaoyang Zeng

Keyword(s):

Decision Tree ◽

Adaptive Algorithms ◽

Memory Access ◽

Access Time ◽

Decision Tree Algorithm ◽

Verilog Hdl ◽

Tree Model ◽

Cache Associativity ◽

Cache Scheme ◽

Reconfigurable Cache

Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.

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