L 2 C: Combining Lossy and Lossless Compression on Memory and I/O

In this article, we introduce L 2 C, a hybrid lossy/lossless compression scheme applicable both to the memory subsystem and I/O traffic of a processor chip. L 2 C employs general-purpose lossless compression and combines it with state-of-the-art lossy compression to achieve compression ratios up to 16:1 and to improve the utilization of chip’s bandwidth resources. Compressing memory traffic yields lower memory access time, improving system performance, and energy efficiency. Compressing I/O traffic offers several benefits for resource-constrained systems, including more efficient storage and networking. We evaluate L 2 C as a memory compressor in simulation with a set of approximation-tolerant applications. L 2 C improves baseline execution time by an average of 50% and total system energy consumption by 16%. Compared to the lossy and lossless current state-of-the-art memory compression approaches, L 2 C improves execution time by 9% and 26%, respectively, and reduces system energy costs by 3% and 5%, respectively. I/O compression efficacy is evaluated using a set of real-life datasets. L 2 C achieves compression ratios of up to 10.4:1 for a single dataset and on average about 4:1, while introducing no more than 0.4% error.

Percutaneous Transsplenic Balloon-Assisted Transjugular Intrahepatic Portosystemic Shunt Placement in Patients with Portal Vein Obliteration for Portal Vein Recanalization: Feasibility, Safety and Effectiveness

Purpose To assess the feasibility, safety and effectiveness of portal vein recanalization (PVR)–transjugular portosystemic shunt (TIPS) placement via splenic access using a balloon puncture technique. Materials and Methods In a single-center retrospective study from March 2017 to February 2021, 14 consecutive patients with portal hypertension, chronic liver disease and portal vein occlusion or near-complete (> 95%) occlusion were referred for PVR–TIPS placement. Feasibility, safety and effectiveness including procedural characteristics such as technical success, complication profile and splenic access time (SAT), balloon positioning time (BPT), conventional portal vein entry time (CPVET), overall procedure time (OPT), fluoroscopy time (FT), dose–area product (DAP) and air kerma (AK) were evaluated. Results Transsplenic PVR–TIPS using balloon puncture technique was technically feasible in 12 of 14 patients (8 men, 49 ± 13 years). In two patients without detectable intrahepatic portal vein branches, TIPS placement was not feasible and both patients were referred for further treatment with nonselective beta blockers and endoscopic variceal ligation. No complications grade > 3 of the Cardiovascular and Interventional Radiological Society of Europe classification system occurred. The SAT was 25 ± 21 min, CPVET was 33 ± 26 min, the OPT was 158 ± 54 min, the FT was 42 ± 22 min, the DAP was 167.84 ± 129.23 Gy*cm2 and the AK was 1150.70 ± 910.73 mGy. Conclusions Transsplenic PVR–TIPS using a balloon puncture technique is feasible and appears to be safe in our series of patients with obliteration of the portal vein. It expands the interventional options in patients with chronic PVT.

Exploring for Route Preferences of Subway Passengers Using Smart Card and Train Log Data

As the mode share of the subway in Seoul has increased, the estimation of passenger travel routes has become a crucial issue to identify the congestion sections in the subway network. This paper aims to estimate the travel train of subway passengers in Seoul. The alternative routes are generated based on the train log data. The travel route is then estimated by the empirical cumulative distribution functions (ECDFs) of access time, egress time, and transfer time. The train choice probability is estimated for alternative train combinations and the train combination with the highest probability is assigned to the subway passenger. The estimated result is validated using the transfer gate data which are recorded on private subway lines. The result showed that the accuracy of the estimated travel train is shown to be 95.6%. The choice ratios for no-transfer, one-transfer, two-transfer, three-transfer, and four-transfer trips are estimated to be 53.9%, 37.7%, 6.5%, 1.5%, and 0.4%, respectively. Regarding the practical application, the passenger kilometers by lines are estimated with the travel route estimation of the whole network. As results of the passenger kilometer calculation, the passenger kilometer of the proposed algorithm is estimated to be 88,314 million passenger kilometer. The proposed algorithm estimates the passenger kilometer about 13% higher than the shortest path algorithm. This result implies that the passengers do not always prefer the shortest path and detour about 13% for their convenience.

Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell

Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray’s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET’s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.

Energy-Efficient Hybrid Unicore Architecture In Future Embedded Chip-Multiprocessor

Recently, technology scaling has enabled the placement of an increasing number of cores, in the form of chip-multiprocessors (CMPs) on a chip and continually shrinking transistor sizes to improve performance. In this context, power consumption has become the main constraint in designing CMPs. As a result, uncore components power consumption taking increasing portion from the on-chip power budget; therefore, designing power management techniques, particularly memory and network-on-chip (NoC) systems, has become an important issue to solve. Consequently, a considerable attention has been directed toward power management based on CMPs components, particularly shared caches and uncore interconnected structures, to overcome the challenges of limited chip power budget.<div>This work targets to design an energy-efficient uncore architecture by using heterogeneity in components (cache cells) and operational parameters (Voltage/Frequency). In order to ensure the minimum impact on the system performance, a run-time approach is investigated to assess the proposed method. An architecture is proposed where the cache layer contains the heterogenous cache banks in all placed in one frequency voltage domain. Average memory access time (AMAT) was selected as a network monitor to monitor the performance on the run-time. The appropriate size and type of the last level cache (LLC) and Voltage/Frequency for the uncore domain is adjusted according to the calculated AMAT which indicates the system demand from the uncore.<br></div><div>The proposed hybrid architecture was implemented, investigated and compared with the a baseline model where only SRAM banks were used in the last level cache. Experimental results on the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suit,show that the proposed architecture yields up to a 40% reduction in overall chip energy-delay product with a marginal performance degradation in average of -1.2% below the baseline one. The best energy saving was 55% and the worse degradation was only 15%.<br></div>

Energy-Efficient Hybrid Unicore Architecture In Future Embedded Chip-Multiprocessor

Recently, technology scaling has enabled the placement of an increasing number of cores, in the form of chip-multiprocessors (CMPs) on a chip and continually shrinking transistor sizes to improve performance. In this context, power consumption has become the main constraint in designing CMPs. As a result, uncore components power consumption taking increasing portion from the on-chip power budget; therefore, designing power management techniques, particularly memory and network-on-chip (NoC) systems, has become an important issue to solve. Consequently, a considerable attention has been directed toward power management based on CMPs components, particularly shared caches and uncore interconnected structures, to overcome the challenges of limited chip power budget.<div>This work targets to design an energy-efficient uncore architecture by using heterogeneity in components (cache cells) and operational parameters (Voltage/Frequency). In order to ensure the minimum impact on the system performance, a run-time approach is investigated to assess the proposed method. An architecture is proposed where the cache layer contains the heterogenous cache banks in all placed in one frequency voltage domain. Average memory access time (AMAT) was selected as a network monitor to monitor the performance on the run-time. The appropriate size and type of the last level cache (LLC) and Voltage/Frequency for the uncore domain is adjusted according to the calculated AMAT which indicates the system demand from the uncore.<br></div><div>The proposed hybrid architecture was implemented, investigated and compared with the a baseline model where only SRAM banks were used in the last level cache. Experimental results on the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suit,show that the proposed architecture yields up to a 40% reduction in overall chip energy-delay product with a marginal performance degradation in average of -1.2% below the baseline one. The best energy saving was 55% and the worse degradation was only 15%.<br></div>

Sistem Pendukung Keputusan Menentukan Media Yang Tepat Untuk Pembelajaran Secara Online Di SMP Negeri 1 Alasa Talumuzoi Menggunakan Metode AHP

In the world of education, we really need media as a means of interaction between teachers and students to convey information messages in teaching both in the form of written media, image media, sound media, video media, and print media. With the media, students are easier to understand and understand the meaning of the lessons given. The criteria data for the application of the Analytical Hierarchy Process (AHP) method include Ease of Access, Internet Quota Usage, Audio and Visual Interaction, User Limit Capacity, and Access Time Limit. Alternative data for the application of the Analytical Hierarchy Process (AHP) method includes 5 online media, namely Google Classroom, Edmodo Application, Zoom Meeting, Cisco Webex, and Moodle Application. The ranking results on the alternative obtained rank 1, namely Google Classroom Value = 0.4139. The system is designed web-based using PHP and MySQL.

“Motorcycle Ambulance” Policy to Promote Health and Sustainable Development in Large Cities

Introduction: Motorcycles can be considered a new form of smart vehicle when taking into account their small and modern structure and due to the fact that nowadays, they are used in the new role of ambulance to rapidly reach emergency patients in large cities with traffic congestion. However, there is no study regarding the measuring of access time for motorcycle ambulances (motorlances) in large cities of Thailand. Study Objective: This study aims to compare access times to patients between motorlances and conventional ambulances, including analysis of the use of automated external defibrillators (AEDs) installed on motorlances to contribute to the sustainable development of public health policies. Methods: A cross-sectional study was conducted on all motorlance operations in Emergency Medical Services (EMS) at Srinagarind Hospital, Thailand from January 2019 through December 2020. Data were recorded using a national standard operation record form for Thailand. Results: Two hundred seventy-one motorlance operations were examined over a two-year period. A total of 52.4% (N = 142) of the patients were male. The average times from dispatch to vehicle (motorlance and traditional ambulance) being en route (activation time) for motorlance and ambulance in afternoon shift were 0.59 minutes and 1.45 minutes, respectively (P = .004). The average motorlance response time in the afternoon shift was 6.12 minutes, and ambulance response time was 9.10 minutes at the same shift. Almost all of the motorlance operations (97.8%) were found to have no access to AED equipment installed in public areas. The average time from dispatch to AED arrival on scene (AED access time) was 5.02 minutes. Conclusion: The response time of motorlances was shorter than a conventional ambulance, and the use of AEDs on a motorlance can increase the chances of survival for patients with cardiac arrest outside the hospital in public places where AEDs are not available.