Design of Fully Pipelined Dual-Mode Double Precision Reduction Circuit on FPGAs
2017 ◽
Vol 64
(2)
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pp. 386-398
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1996 ◽
Vol 22
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pp. 99
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1987 ◽
Vol 134
(4)
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pp. 369
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2016 ◽
Vol 26
(4)
◽
pp. 319-347
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2012 ◽
Vol 11
(6)
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pp. 487-510
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