Solving Standard Cell Placement Problem Using Discrete Firefly Algorithm: A Nature Inspired Approach

2016 ◽  
pp. 380-384
Author(s):  
Pradip Kumar Sharma ◽  
Saurabh Singh ◽  
Jong Hyuk Park
Keyword(s):  
Firefly Algorithm ◽  
Standard Cell ◽  
Placement Problem ◽  
Discrete Firefly Algorithm ◽  
Cell Placement

scholarly journals A Swarm Random Walk Based Method for the Standard Cell Placement Problem

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Najwa Altwaijry ◽  
Mohamed El Bachir Menai
Keyword(s):  
Simulated Annealing ◽  
Random Walk ◽  
Hybrid Methods ◽  
Vlsi Design ◽  
Standard Cell ◽  
Placement Problem ◽  
Benchmark Suite ◽  
Cell Placement ◽  
On Chip ◽  
Min Cut

The standard cell placement (SCP) problem is a well-studied placement problem, as it is an important step in the VLSI design process. In SCP, cells are placed on chip to optimize some objectives, such as wirelength or area. The SCP problem is solved using mainly four basic methods: simulated annealing, quadratic placement, min-cut placement, and force-directed placement. These methods are adequate for small chip sizes. Nowadays, chip sizes are very large, and hence, hybrid methods are employed to solve the SCP problem instead of the original methods by themselves. This paper presents a new hybrid method for the SCP problem using a swarm intelligence-based (SI) method, called SwarmRW (swarm random walk), on top of a min-cut based partitioner. The resulting placer, called sPL (swarm placer), was tested on the PEKU benchmark suite and compared with several related placers. The obtained results demonstrate the effectiveness of the proposed approach and show that sPL can achieve competitive performance.

INTERCONNECTION WIRE-LENGTH ESTIMATION IN VLSI STANDARD CELL PLACEMENT VIA NEURAL NETWORK

1998 ◽  
Vol 07 (04) ◽  
pp. 443-451 ◽  
Author(s):  
ASHUTOSH SAXENA ◽  
SUJU M. GEORGE ◽  
P. RAMBABU
Keyword(s):  
Neural Network ◽  
Standard Cell ◽  
Wire Length ◽  
Placement Problem ◽  
Network Characteristics ◽  
Length Estimation ◽  
Input And Output ◽  
The Neural Network ◽  
Cell Placement ◽  
Inaccurate Estimate

Neural Network is used as a tool for estimating interconnection wire-length in VLSI standard cell placement problem. Conventional methods for estimating the interconnection wire-length viz., Bounding Rectangle method, provide inaccurate estimate of the interconnection wire-length and does not depict the interconnection procedure in a layout and separates routing and placement tasks distinctly. The proposed mechanism utilizes the neural network characteristics in understanding the functional mapping between input and output, to estimate the interconnection wire-length. Experiments were performed for different number of cells with varying complexity of interconnections. In all the cases, the performance of the Neural Network is found to be superior to the results obtained using Bounding Rectangle procedure.

scholarly journals IFDR: An Efficient Iterative Optimization Algorithm for Standard Cell Placement

2004 ◽  
Vol 27 (4) ◽  
pp. 189-195
Author(s):  
Feng Cheng ◽  
Junfa Mao
Keyword(s):  
Integrated Circuits ◽  
Optimization Algorithm ◽  
Electrical Circuit ◽  
Standard Cell ◽  
Placement Problem ◽  
Iterative Optimization ◽  
Automatic Placement ◽  
Cell Placement ◽  
Placement Algorithm ◽  
Iterative Optimization Algorithm

In the automatic placement of integrated circuits, the force directed relaxation (FDR) method [Goto, S. (1981). An efficient algorithm for the two-dimensional placement problem in electrical circuit layout.IEEE Trans. on Circuits and Systems,CAS-28(1), 12-18] is a good iterative optimization algorithm. In this article, an improved force directed relaxation (IFDR) method for standard cell placement is presented, which provides a more flexible and efficient cell location adjustment scheme and a more extensive searching scale for better iterative placement optimization than the FDR method. A new heuristic algorithm based on local optimization is combined with the IFDR method to improve the placement. Experiments on the Microelectronics Center of North Carolina (MCNC) standard cell benchmarks [http://www.cbl.ncsu.edu/pub/Benchmark_ dirs/Layout Synth92/] have been done, and the results show that total wire length is reduced up to 25% and by an average of 16% in comparison with that from the placement algorithm of TimberWolf7.0.

scholarly journals Mathematical Modeling and Discrete Firefly Algorithm to Optimize Scheduling Problem with Release Date, Sequence-Dependent Setup Time, and Periodic Maintenance

2019 ◽  
Vol 2019 ◽  
pp. 1-16 ◽  
Author(s):  
Mustafa A. Qamhan ◽  
Ammar A. Qamhan ◽  
Ibrahim M. Al-Harkan ◽  
Yousef A. Alotaibi
Keyword(s):  
Firefly Algorithm ◽  
Programming Model ◽  
Setup Time ◽  
Mixed Integer ◽  
Release Date ◽  
Sequence Dependent ◽  
Sequence Dependent Setup Time ◽  
Periodic Maintenance ◽  
Discrete Firefly Algorithm ◽  
Sequence Dependent Setup

An evolutionary discrete firefly algorithm (EDFA) is presented herein to solve a real-world manufacturing system problem of scheduling a set of jobs on a single machine subject to nonzero release date, sequence-dependent setup time, and periodic maintenance with the objective of minimizing the maximum completion time “makespan.” To evaluate the performance of the proposed EDFA, a new mixed-integer linear programming model is also proposed for small-sized instances. Furthermore, the parameters of the EDFA are regulated using full factorial analysis. Finally, numerical experiments are performed to demonstrate the efficiency and capability of the EDFA in solving the abovementioned problem.

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