A Double-Boost Converter Based on Coupled Inductance and Magnetic Integration

High-voltage gain converter has a high-frequency use in some industrial fields, for instance, the fuel cell system, the photovoltaic system, electric vehicles, and the high-intensity discharge lamp. In order to solve the problem of the low-voltage gain of traditional boost converter, the double-boost converter with coupled inductance and doubled voltage is proposed, which connects the traditional boost converter in parallel. The voltage gain of the converter is further improved by introducing the voltage-doubled unit of the coupled inductance. Moreover, the clamp capacitor can absorb the leakage inductance in the circuit and reduce the voltage stress of the switch. In addition, two coupled inductors are magnetically collected; then, the loss of the core is analyzed under the same gain. The detailed analysis of the proposed converter and a comparison considering other topologies previously published in the literature are also presented in this article. In order to verify the proposed converter performance, a prototype has been built for a power of 200 W, input and output voltages of 12 and 84 V, respectively, and a switching frequency of 50 kHz. Experimental results validate the effectiveness of the theoretical analysis proving the satisfactory converter performance, whose peak efficiency is 95.5%.

A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior

In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.

A Novel Passive Circuit Emulator for a Current-Controlled Memristor

A memristor is an electrical element, which has been conjectured in 1971 to complete the lumped circuit theory. Currently, researchers use memristor emulators through diodes, inductors, and other passive (or active) elements to study circuits with possible attractors, chaos, and ways of implementing nonlinear transformations for low-voltage novel computing paradigms. However, to date, such passive memristor emulators have been voltage-controlled. In this study, a novel circuit realization of a passive current-controlled passive inductorless emulator is established. It overcomes the lack of passive current-controlled memristor commercial devices, and it can be used as part of more sophisticated circuits. Moreover, it covers a gap in the state of the art because, currently, only passive circuit voltage-controlled memristor emulators and active current-controlled emulators have been developed and used. The emulator only uses two diodes, two resistors, and one capacitance and is passive. The formal theory and simulations validate the proposed circuit, and experimental measurements were performed. The parameter conditions of numerical simulations and experiments are consistent. Simulations were performed with an input current amplitude of 15 mA and frequencies of up to 3 kHz and measurements were carried out with an input current amplitude of 0.74 mA and frequency of 1.5 kHz in order to compare with the state of the art.

A Comparative Study of Over-Current Sensing for Traction Inverters

The over-current condition for a traction inverter can indicate flaws on control algorithms, interference on logic signals, hardware aging, or hardware misconduct. Thus, proper detection of over-current conditions during inverter operation is a critical item for inverter development and product validation. This paper reviews several widely used over-current detection methods and a few theoretically approved over-current detection methods. The main focus of this review includes the sensing bandwidth, sensing accuracy, and implementation complexity of the studied over-current detection methods. The advantages of those widely used methods and the application requirements for the theoretically and prototypingly approved methods are concluded by this review.

Design, Simulation, and Experimental Verification of a Destruction Mechanism of Transient Electronic Devices

To quickly destroy electronic devices and ensure information security, a destruction mechanism of transient electronic devices was designed in this paper. By placing the Ni-Cr film resistance and the energetic material between the chip and the package and heating the resistance by an electric current, the energetic material expanded and the chip cracked. The information on the chip was destroyed. The author simulated the temperature distribution and stress of the power-on structure in different sizes by ANSYS software. The simulation results indicate that the chip cracks within 50 ms under the trigger current of 0.5 A when a circular groove with an area of 1 mm2 and depth of 0.1 mm is filled with an expansion material with an expansion coefficient of 10−5°C−1. Then, the author prepared a sample for experimental verification. Experimental results show that the sample chip quickly cracks and fails within 10 ms under the trigger current of 1 A. The simulation and experimental results confirm the feasibility of the structure in quick destruction, which lays the foundation for developing instantaneous-failure integrated circuit products to meet information security applications.

Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs

Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.

Development of a 100 mW-Class 94 GHz High-Efficiency Single-Series Rectifier Feed by Finline for Micro-UAV Application

Wireless power transfer (WPT) is one solution to realize long flight times and accommodate various missions of micro-uncrewed aerial vehicles (MAVs). Reducing the constraint of power transmission distance and realizing high beam efficiency are possible because of the high directivity of WPT using millimeter wave (MMW) methods. Nevertheless, no report of the relevant literature describes an investigation of sending power to an MAV using MMW because MMW rectennas have low efficiency. The purpose of our study is to conduct fundamental research of a high-efficiency and high-power rectenna at 94 GHz aimed at MAV application using MMW. As described herein, we developed and evaluated a 100-mW-class single-diode rectifier at 94 GHz with a finline of a waveguide (WG) to a microstrip-line (MSL) transducer. With the optimum load of 150 Ω at input power of 128 mW, the output DC power and rectifying efficiency were obtained respectively as 41.7 mW and 32.5%. By comparison to an earlier study, measurement of 94 GHz rectifiers under high power input becomes more accurate through this study.

The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology

The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.

Four-Port Dual-Mode Diplexer with High Signal Isolation

An ease of four-port dual-mode diplexer with high signal isolation is presented. A compact dual-mode diplexer with high signal isolation between the Rx and Tx modules is achievable by only using one resonator filter topology. Two back-to-back dual-mode diplexers have a 180° phase shift in one branch. The high isolation can be achieved by amplitude and phase cancellation technique. The delayed transmission line can be easily achieved by the phase shifter. The simulated and measured four-port dual-mode diplexers are designed at the centre frequency of Rx/Tx at 1.95 GHz and 2.14 GHz, respectively. The measured results of Rx/Tx dual-mode diplexer devices are presented with 47.1 dB Rx/Tx isolation. This four-port dual-mode diplexer achieves the isolation (S32) of more than 24.1 dB when compared with the conventional three-port dual-mode diplexer structure.

Design Tradeoff of Hot Carrier Immunity and Robustness in LDMOS with Grounded Gate Shield

LDMOS devices with grounded gate shield structures variations were simulated and tested, aiming to address hot carrier immunity and robustness concurrently. Optimal configuration of grounded gate shield structure was found to reduce local electrical field strength at gate-to-drain overlap for better hot carrier immunity, and to achieve uniform E-field distribution on drain side for robustness as well. Design trade off of hot carrier immunity (HCI) and robustness is analyzed by simulation and silicon data.