Automatic FPGA Placement Configuration for Customer Designs

Searching for new ways to improve the efficiency of integrated circuits (IC) led to the development of specialized heterogeneous configurable IC (FPGA) and systems-on-a-chip. Their key feature is an extended interpretation of standard cell library, containing ready-to-use IP cores along with standard cells. Specific customer designs require the flexibility of the configurable heterogeneous IC’s architecture and, therefore, automatic CAD clustering and placement algorithms configuration. The development of efficient configuration methods and algorithms is impossible without relying on the mathematical apparatus. In this work, such mathematical apparatus is provided. The authors described a set-theoretic model of a hierarchical project and formalized the hierarchical approach to the netlist, using the apparatus of mathematical logic, set and graph theories. The correspondence between the customers designs’ elements and FPGA’s elements has been formalized to provide fast clustering and placement configuration. The obtained results provide the basis for future efficient methods for automatic placement and clustering configuration.

Study of Allowable Interlaminar Normal Stress Based on the Time–Temperature Equivalence Principle in Automated Fiber Placement Process

Automatic fiber placement (AFP) is a type of labor-saving automatic technology for forming composite materials that are widely used in aviation and other fields. In this process, concave surface delamination is a common defect, as existing research on the conditions for this defect to occur is insufficient. To predict the occurrence of this defect, the concept of allowable interlaminar normal stress is proposed to define its occurrence conditions, and based on this concept, probe tests are carried out using the principle of time–temperature equivalence. Through the laying speed/allowable normal stress curve measured in the probe experiment, the physical meaning of allowable normal stress is discussed. At the same time, the measured curve is quantitatively analyzed, combined with viscoelastic theory and the molecular diffusion reptation model, and the dominating effect in the formation of a metal/prepreg layer and prepreg/prepreg layer is determined. Finally, the experimental data are used to guide the parameter selection in an automatic placement engineering case and prove its correctness.

VISUAL-GRAPHIC PROGRAMMING SYSTEM BASED ON DEVELOPMENT OF ALGORITHM BLOCK SCHEMES. SPATIAL PLACEMENT OF SYMBOLS-BLOCKS OF COMPLEX ALGORITHMS

В работе приведены результаты исследования и разработки редактора блок-схем алгоритмов. Редактор представляет собой один из компонентов проектируемой многоязыковой визуально-графической системы программирования. При ее разработке приходится решать ряд сложных задач, в числе которых – задача автоматического размещения текущего представления элементов (блоков, контейнеров) и связей между ними, в окне, наложенном на потенциально значительно большую по размерам блок-схему проектируемого алгоритма. Способ представления (свернутый или развернутый) каждого контейнера блок-схемы, возможно, содержащего десятки или сотни вложенных в него элементов, на каждом шаге проектирования алгоритма, может выбираться пользователем. Предложен и описан способ пространственного размещения элементов/контейнеров сложных алгоритмов в автоматическом режиме с учетом необходимости реализации всех потенциально возможных операций пользователя по модификации проектируемой блок-схемы. Рассмотрены необходимые для реализации этого подхода внутренние структуры данных визуально-графического редактора и некоторые наиболее важные алгоритмы расчета/пересчета координат блоков/контейнеров и связей между ними в процессе автоматического размещения. The article presents the results of research and development of the algorithm block diagram editor. The editor is one of the components of the projected multilingual visual-graphic programming system. When developing it, it is necessary to solve a number of complex problems, including the problem of automatic placement of the representation of elements (blocks, containers) and links between them in a window superimposed on a large-sized block diagram of an object. predictable algorithm. The presentation method (collapsed or expanded) of each container of the flowchart, which can contain tens or hundreds of nested elements, can be selected by the user at each stage of the algorithm development. A method of spatial arrangement of elements / containers of complex algorithms in automatic mode is proposed and described, taking into account the implementation of all possible user actions to modify the projected block diagram. The necessary approaches for their implementation are the internal data structures of the visual-graphic editor and some of the most important algorithms for calculating / recalculating the coordinates of blocks / containers and the links between them in the process of automatic placement.

Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling

True Random Number Generators (TRNGs) are indispensable in modern cryptosystems. Unfortunately, to guarantee high entropy of the generated numbers, many TRNG designs require a complex implementation procedure, often involving manual placement and routing. In this work, we introduce, analyse, and compare three dynamic calibration mechanisms for the COherent Sampling ring Oscillator based TRNG: GateVar , WireVar , and LUTVar , enabling easy integration of the entropy source into complex systems. The TRNG setup procedure automatically selects a configuration that guarantees the security requirements. In the experiments, we show that two out of the three proposed mechanisms are capable of assuring correct TRNG operation even when an automatic placement is carried out and when the design is ported to another Field-Programmable Gate Array (FPGA) family. We generated random bits on both a Xilinx Spartan 7 and a Microsemi SmartFusion2 implementation that, without post processing, passed the AIS-31 statistical tests at a throughput of 4.65 Mbit/s and 1.47 Mbit/s, respectively.

Quantum Chemical Microsolvation by Automated Water Placement

We developed a quantitative approach to quantum chemical microsolvation. Key in our methodology is the automatic placement of individual solvent molecules based on the free energy solvation thermodynamics derived from molecular dynamics (MD) simulations and grid inhomogeneous solvation theory (GIST). This protocol enabled us to rigorously define the number, position, and orientation of individual solvent molecules and to determine their interaction with the solute based on physical quantities. The generated solute–solvent clusters served as an input for subsequent quantum chemical investigations. We showcased the applicability, scope, and limitations of this computational approach for a number of small molecules, including urea, 2-aminobenzothiazole, (+)-syn-benzotriborneol, benzoic acid, and helicene. Our results show excellent agreement with the available ab initio molecular dynamics data and experimental results.

An analysis of ADPLL applications in various fields

<span>ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a phase detector, loop filter and digital controlled oscillator. The conventional PLL and digital PLL used for frequency synthesis, clock recovery circuit and synchronization give imprecise performance with respect to reliability, speed, power consumption, noise, locking speed, cost, etc. ADPLL overcomes the drawbacks of conventional PLL and digital PLL. In this paper, different approaches followed in All Digital Phase Locked Loop (ADPLL) for various applications are reviewed and their performance is compared based on components, modulation functions, frequency range, power utilization etc. In addition, an ADPLL with wide tuning range and frequency resolution is designed and implemented using automatic placement and routing, time to digital converter, digital loop filter and ring based oscillator. The ADPLL outputs and the results are analyzed with micro wind tool. The design gives a frequency range from 1.0-5.5GHz with low power consumption and it can also be used for Clock generation applications. </span>