FPGA Implementation of LDPC Decoder

2020 ◽  
pp. 399-411
Author(s):  
Shruti ◽  
Barathram Ramkumar
Keyword(s):  
Fpga Implementation ◽  
Ldpc Decoder

scholarly journals Memory Compact High-Speed QC-LDPC Decoder Based on FPGA

2019 ◽  
Vol 37 (3) ◽  
pp. 515-522
Author(s):  
Tianjiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Fpga Implementation ◽  
Maximum Frequency ◽  
Ldpc Decoder ◽  
Memory Strategies ◽  
Multiple Data ◽  
Decoder Architecture ◽  
Place And Route ◽  
Area Efficient

In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

Efficient FPGA implementation of probabilistic gallager B LDPC decoder

2017 ◽  
Author(s):  
Fakhreddine Ghaffari ◽  
Burak Unal ◽  
Ali Akoglu ◽  
Khoa Le ◽  
David Declercq ◽  
...  
Keyword(s):  
Fpga Implementation ◽  
Ldpc Decoder
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