Efficient FPGA Implementation of FIR Filter Using Distributed Arithmetic

2020 ◽  
pp. 151-160
Author(s):  
Debarshi Datta ◽  
Himadri Sekhar Dutta
Keyword(s):  
Fir Filter ◽  
Fpga Implementation ◽  
Distributed Arithmetic

A Design of VB-DDC Using DA-Based Systolic FIR Filter

2011 ◽  
Vol 130-134 ◽  
pp. 3950-3953
Author(s):  
Ping Xu ◽  
Wei Xia ◽  
Zi Shu He
Keyword(s):  
Fir Filter ◽  
Fpga Implementation ◽  
Distributed Arithmetic ◽  
Shaping Filter ◽  
Variable Bandwidth ◽  
Digital Down Converter ◽  
Systolic Structure ◽  
Computing Structure

In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.

Design of FIR Filter for Efficient FPGA Implementation

2015 ◽  
Vol 5 (3) ◽  
pp. 1-10
Author(s):  
S. V. Padmajarani ◽  
◽  
M. Muralidhar ◽  
Keyword(s):  
Fir Filter ◽  
Fpga Implementation

Low power area efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture

2020 ◽  
Vol 23 (2) ◽  
pp. 287-296 ◽  
Author(s):  
P. V. Praveen Sundar ◽  
D. Ranjith ◽  
T. Karthikeyan ◽  
V. Vinoth Kumar ◽  
Balajee Jeyakumar
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Adaptive Fir ◽  
Area Efficient
Sign in / Sign up

Export Citation Format

Share Document