scholarly journals Implementation of High Speed Pipelined Distributed Arithmetic Based FIR Filter

2015 ◽  
Vol 11 (12) ◽  
pp. 1404-1409 ◽  
Author(s):  
P.L. Joseph Raj ◽  
T. Vigneswaran
2011 ◽  
Vol 25 (7) ◽  
pp. 26-32 ◽  
Author(s):  
Narendra Singh Pal ◽  
Harjit Pal Singh ◽  
R.K. Sarin ◽  
Sarabjeet Singh

2020 ◽  
Vol 23 (2) ◽  
pp. 259-264 ◽  
Author(s):  
Grande Naga Jyothi ◽  
Kishore Sanapala ◽  
A. Vijayalakshmi

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.


Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.


Sign in / Sign up

Export Citation Format

Share Document