Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults

1995 ◽  
Vol 7 (3) ◽  
pp. 209-221 ◽  
Author(s):  
Shujian Zhang ◽  
Rod Byrne ◽  
Jon C. Muzio ◽  
D. Michael Miller

1990 ◽  
Vol 34 (2.3) ◽  
pp. 389-405 ◽  
Author(s):  
P. D. Hortensius ◽  
R. D. McLeod ◽  
B. W. Podaima


2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.





1995 ◽  
Vol 44 (6) ◽  
pp. 805-816 ◽  
Author(s):  
S. Boubezari ◽  
B. Kaminska




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