Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)
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Enhancing test effectiveness for analog circuits using synthesized measurements

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670860 ◽

2002 ◽

Cited By ~ 65

Author(s):

P.N. Variyam ◽

A. Chatterjee

Keyword(s):

Analog Circuits

Effect of noise on analog circuit testing

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670861 ◽

2002 ◽

Cited By ~ 3

Author(s):

M.K. Iyer ◽

M.L. Bushnell

Keyword(s):

Analog Circuit ◽

Circuit Testing ◽

Analog Circuit Testing

On the identification of optimal cellular automata for built-in self-test of sequential circuits

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670902 ◽

2002 ◽

Cited By ~ 4

Author(s):

F. Corno ◽

N. Gaudenzi ◽

P. Prinetto ◽

M.S. Reorda

Keyword(s):

Cellular Automata ◽

Sequential Circuits ◽

Self Test ◽

Built In Self Test

Using verification technology for validation coverage analysis and test generation

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670877 ◽

2002 ◽

Author(s):

D. Moundanos ◽

J.A. Abraham

Keyword(s):

Test Generation ◽

Coverage Analysis

Designing a testable system on a chip

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670841 ◽

2002 ◽

Cited By ~ 1

Author(s):

S.V. Kosonocky ◽

A. Bright ◽

K. Warren ◽

R.A. Haring ◽

S. Klepner ◽

...

Keyword(s):

System On A Chip

Automatic test pattern generation for crosstalk glitches in digital circuits

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670846 ◽

2002 ◽

Author(s):

Kyung Tek Lee ◽

C. Nordquist ◽

J.A. Abraham

Keyword(s):

Digital Circuits ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Automatic Test

An introduction to RF testing: device, method and system

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670913 ◽

2002 ◽

Cited By ~ 4

Author(s):

J.S. Kasten ◽

B. Kaminska

Keyword(s):

Testing Device ◽

Rf Testing

Efficient path selection for delay testing based on partial path evaluation

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670867 ◽

2002 ◽

Cited By ~ 27

Author(s):

S. Tani ◽

M. Teramoto ◽

T. Fukazawa ◽

K. Matsuhiro

Keyword(s):

Path Selection ◽

Delay Testing ◽

Selection For ◽

Partial Path

Synthesis of zero-aliasing elementary-tree space compactors

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670851 ◽

2002 ◽

Cited By ~ 54

Author(s):

B. Pouya ◽

N.A. Touba

Keyword(s):

Tree Space

A methodology for transforming memory tests for in-system testing of direct mapped cache tags

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670897 ◽

2002 ◽

Cited By ~ 14

Author(s):

S.M. Al-Harbi ◽

S.K. Gupta

Keyword(s):

System Testing ◽

Memory Tests

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Enhancing test effectiveness for analog circuits using synthesized measurements

Effect of noise on analog circuit testing

On the identification of optimal cellular automata for built-in self-test of sequential circuits

Using verification technology for validation coverage analysis and test generation

Designing a testable system on a chip

Automatic test pattern generation for crosstalk glitches in digital circuits

An introduction to RF testing: device, method and system

Efficient path selection for delay testing based on partial path evaluation

Synthesis of zero-aliasing elementary-tree space compactors

A methodology for transforming memory tests for in-system testing of direct mapped cache tags

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)
Latest Publications