Design and implementation of higher order sigma delta modulator circuits using FPAA

2020 ◽  
Vol 104 (2) ◽  
pp. 169-182
Author(s):  
Daisy Deenrii Roel ◽  
Manoj Kumar
2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.


2018 ◽  
Vol 39 (5) ◽  
pp. 055002
Author(s):  
Binjie Ge ◽  
Yan Li ◽  
Hang Yu ◽  
Xiaoxing Feng

2008 ◽  
Vol 58 (3) ◽  
pp. 243-253 ◽  
Author(s):  
Enrique Prefasi ◽  
Luis Hernandez ◽  
Stijn Reekmans ◽  
Pieter Rombouts

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