Dual low-power and crosstalk immune encoding scheme for on-chip data buses

Electronics Letters ◽

10.1049/el:20030934 ◽

2003 ◽

Vol 39 (20) ◽

pp. 1436 ◽

Author(s):

Z. Khan ◽

A.T. Erdogan ◽

T. Arslan

Keyword(s):

Low Power ◽

Encoding Scheme ◽

Chip Data ◽

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Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses

Designs Codes and Cryptography ◽

10.1007/s10623-015-0084-4 ◽

2015 ◽

Vol 77 (2-3) ◽

pp. 479-491 ◽

Author(s):

Yeow Meng Chee ◽

Charles J. Colbourn ◽

Alan Chi Hung Ling ◽

Hui Zhang ◽

Xiande Zhang

Keyword(s):

Low Power ◽

Error Correction ◽

Chip Data ◽

On Chip ◽

Crosstalk Avoidance

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Low power error resilient encoding for on-chip data buses

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2002.998256 ◽

2003 ◽

Author(s):

D. Bertozzi ◽

L. Benini ◽

G. De Micheli

Keyword(s):

Low Power ◽

Error Resilient ◽

Chip Data ◽

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Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2006.342072 ◽

2006 ◽

Author(s):

Qingli Zhang ◽

Jinxiang Wang ◽

Yizheng Ye

Keyword(s):

Low Power ◽

Chip Data ◽

On Chip ◽

Crosstalk Avoidance

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New Methodology for Combined Simulation of Delta-I Noise Interaction With Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power-Blocks

IEEE Transactions on Advanced Packaging ◽

10.1109/tadvp.2005.862647 ◽

2006 ◽

Vol 29 (1) ◽

pp. 11-20 ◽

Author(s):

A. Deutsch ◽

H.H. Smith ◽

B.J. Rubin ◽

B.L. Krauter ◽

G.V. Kopcsay

Keyword(s):

Transmission Line ◽

Chip Data ◽

Lossy Transmission ◽

Combined Simulation ◽

On Chip ◽

Lossy Transmission Line ◽

Interconnect Noise

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Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1093/ietfec/e88-a.12.3282 ◽

2005 ◽

Vol E88-A (12) ◽

pp. 3282-3289 ◽

Author(s):

S. KOMATSU

Keyword(s):

Low Power ◽

Data Transfer ◽

Fault Tolerant ◽

Chip Data ◽

Practical Applications ◽

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A Novel Encoding Scheme for Low Power in Network on Chip Links

2012 25th International Conference on VLSI Design ◽

10.1109/vlsid.2012.80 ◽

2012 ◽

Author(s):

Deepa N. Sarma ◽

G. Lakshminarayanan ◽

K.V.R. Suryakiran Chavali

Keyword(s):

Low Power ◽

Network On Chip ◽

Encoding Scheme ◽

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A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-30205-6_60 ◽

2004 ◽

pp. 585-592 ◽

Author(s):

Zahid Khan ◽

Tughrul Arslan ◽

Ahmet T. Erdogan

Keyword(s):

Low Power ◽

System On Chip ◽

Encoding Scheme ◽

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Methodology to simulate delta-I noise interaction with interconnect noise for wide, on-chip data-buses using lossy transmission-line power-blocks

Electrical Performance of Electronic Packaging EPEP-04 ◽

10.1109/epep.2004.1407615 ◽

2005 ◽

Author(s):

A. Deutsch ◽

H.H. Smith ◽

B.J. Rubin ◽

B.L. Krauter ◽

G.V. Kopcsay

Keyword(s):

Transmission Line ◽

Chip Data ◽

Lossy Transmission ◽

On Chip ◽

Lossy Transmission Line ◽

Interconnect Noise

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A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters

2000 Digest of Technical Papers. International Conference on Consumer Electronics. Nineteenth in the Series (Cat. No.00CH37102) ◽

10.1109/icce.2000.854617 ◽

2002 ◽

Author(s):

Sekyoung Hong ◽

Byungcheol Park ◽

Dalsoo Kim ◽

Minkyu Song

Keyword(s):

Low Power ◽

Data Converters ◽

Chip Data ◽

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Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320060 ◽

2006 ◽

Author(s):

Yeow Chee ◽

Charles Colbourn ◽

Alan H. Ling

Keyword(s):

Low Power ◽

Chip Data ◽

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