Reliability aware throughput management of chip multi-processor architecture via thread migration

Fatemeh Pouyan; Ali Azarpeyvand; Saeed Safari; Sied Mehdi Fakhraie

doi:10.1007/s11227-016-1665-3

Reliability aware throughput management of chip multi-processor architecture via thread migration

The Journal of Supercomputing ◽

10.1007/s11227-016-1665-3 ◽

2016 ◽

Vol 72 (4) ◽

pp. 1363-1380 ◽

Cited By ~ 2

Author(s):

Fatemeh Pouyan ◽

Ali Azarpeyvand ◽

Saeed Safari ◽

Sied Mehdi Fakhraie

Keyword(s):

Processor Architecture ◽

Thread Migration

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Thread Migration and Communication Minimization in DSM Systems

10.21236/ada377024 ◽

1998 ◽

Cited By ~ 1

Author(s):

Kritchalach Thitikamol ◽

Pete Keleher

Keyword(s):

Thread Migration

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Customising a processor architecture for multimedia applications

Electronic Systems and Software ◽

10.1049/ess:20030406 ◽

2003 ◽

Vol 1 (4) ◽

pp. 29-33 ◽

Cited By ~ 1

Author(s):

H. Eichel

Keyword(s):

Multimedia Applications ◽

Processor Architecture

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Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets

2020 16th International Conference on Control, Automation, Robotics and Vision (ICARCV) ◽

10.1109/icarcv50220.2020.9305402 ◽

2020 ◽

Author(s):

Maciej Kopczynski ◽

Tomasz Grzes

Keyword(s):

Rough Set ◽

Processor Architecture

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Towards Efficient Superconducting Quantum Processor Architecture Design

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems ◽

10.1145/3373376.3378500 ◽

2020 ◽

Cited By ~ 4

Author(s):

Gushu Li ◽

Yufei Ding ◽

Yuan Xie

Keyword(s):

Architecture Design ◽

Processor Architecture ◽

Quantum Processor

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How to make your own processor architecture (review of Processor Design: System-on-Chip Computing for ASICs and FPGAs by Nurmi, J., Ed.; 2007) [Book reviews]

IEEE Design & Test of Computers ◽

10.1109/mdt.2008.14 ◽

2008 ◽

Vol 25 (1) ◽

pp. 96-98

Author(s):

Scott Davidson

Keyword(s):

System On Chip ◽

Design System ◽

Processor Architecture ◽

Processor Design ◽

On Chip

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QrnPro: New Processor Architecture for Accelerating Quran Applications

2013 Taibah University International Conference on Advances in Information Technology for the Holy Quran and Its Sciences ◽

10.1109/nooric.2013.89 ◽

2013 ◽

Cited By ~ 1

Author(s):

Mostafa I. Soliman

Keyword(s):

Processor Architecture

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Job Scheduling in Multi Processor Architecture Using Genetic Algorithm

2007 Innovations in Information Technologies (IIT) ◽

10.1109/iit.2007.4430439 ◽

2007 ◽

Cited By ~ 6

Author(s):

Elnaz Zafarani Moattar ◽

Amir Masoud Rahmani ◽

Mohammad Reza Feizi Derakhshi

Keyword(s):

Genetic Algorithm ◽

Job Scheduling ◽

Processor Architecture

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MASA: a multithreaded processor architecture for parallel symbolic computing

[1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings ◽

10.1109/isca.1988.5255 ◽

2003 ◽

Cited By ~ 46

Author(s):

R.H. Halstead ◽

T. Fujita

Keyword(s):

Processor Architecture ◽

Symbolic Computing ◽

Multithreaded Processor

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The K2 parallel processor: architecture and hardware implementation

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134512 ◽

2002 ◽

Cited By ~ 6

Author(s):

M. Annaratone ◽

M. Fillo ◽

K. Nakabayashi ◽

M. Viredaz

Keyword(s):

Hardware Implementation ◽

Processor Architecture ◽

Parallel Processor

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Low power sensor node processor architecture

2010 17th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2010.5724661 ◽

2010 ◽

Cited By ~ 3

Author(s):

Goran Panic ◽

Thomas Basmer ◽

Klaus Tittelbach-Helmrich ◽

Lukasz Lopacinski

Keyword(s):

Low Power ◽

Sensor Node ◽

Processor Architecture ◽

Power Sensor

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