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Communication-aware branch and bound with cluster-based latency-constraint mapping technique on network-on-chip
The Journal of Supercomputing
◽
10.1007/s11227-016-1732-9
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2016
◽
Vol 72
(6)
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pp. 2283-2309
◽
Cited By ~ 1
Author(s):
Ke Pang
◽
Virginie Fresse
◽
Suying Yao
Keyword(s):
Branch And Bound
◽
Network On Chip
◽
Mapping Technique
◽
Constraint Mapping
◽
On Chip
Download Full-text
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Cited By
References
Energy consumption and performance comparison of DE optimization and PSO based IP core mapping technique for 2-D and 3-D network-on-chip
Semiconductor Science and Technology
◽
10.1088/1361-6641/ac038c
◽
2021
◽
Author(s):
Jayshree
◽
Gopalakrishnan Seetharaman
◽
Debadatta Pati
Keyword(s):
Energy Consumption
◽
Network On Chip
◽
Performance Comparison
◽
Mapping Technique
◽
Ip Core
◽
And Performance
◽
On Chip
◽
Core Mapping
Download Full-text
An Application Mapping Technique for Butterfly-Fat-Tree Network-on-Chip
2011 Second International Conference on Emerging Applications of Information Technology
◽
10.1109/eait.2011.37
◽
2011
◽
Cited By ~ 9
Author(s):
Pradip Kumar Sahu
◽
Nisarg Shah
◽
Kanchan Manna
◽
Santanu Chattopadhyay
Keyword(s):
Network On Chip
◽
Mapping Technique
◽
Tree Network
◽
Application Mapping
◽
On Chip
Download Full-text
Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm
2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
◽
10.1109/pdp.2013.81
◽
2013
◽
Cited By ~ 1
Author(s):
A. Eskandari
◽
A. Khademzadeh
◽
N. Bagherzadeh
◽
M. Janidarmian
Keyword(s):
Quality Of Service
◽
Network On Chip
◽
Mapping Algorithm
◽
Bandwidth Constraint
◽
Constraint Mapping
◽
On Chip
◽
Service Optimization
Download Full-text
Application of exhaustive search, branch and bound, parallel computing and Monte-Carlo methods for the synthesis of quasi-optimal network-on-chip topologies
2017 IEEE East-West Design & Test Symposium (EWDTS)
◽
10.1109/ewdts.2017.8110092
◽
2017
◽
Cited By ~ 1
Author(s):
Aleksandr Romanov
◽
Irina Romanova
◽
Alexander Ivannikov
Keyword(s):
Monte Carlo
◽
Parallel Computing
◽
Branch And Bound
◽
Monte Carlo Methods
◽
Network On Chip
◽
Exhaustive Search
◽
Optimal Network
◽
On Chip
Download Full-text
Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders
Oct. 17-19, 2017 Dubai (UAE)
◽
10.15242/dirpub.dir1017020
◽
2018
◽
Keyword(s):
Real Time
◽
Network On Chip
◽
On Chip
Download Full-text
A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs
Artificial Intelligence and Industrial Application
◽
10.2495/aiia140551
◽
2015
◽
Author(s):
J. Fang
◽
L. Yu
◽
Z. Y. Leng
Keyword(s):
Routing Algorithm
◽
Network On Chip
◽
Tree Architecture
◽
On Chip
◽
Congestion Aware
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VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications
i-manager’s Journal on Electronics Engineering
◽
10.26634/jele.5.1.3320
◽
2014
◽
Vol 5
(1)
◽
pp. 27-32
Author(s):
Jeeva Anusha
◽
◽
V. Thrimurthulu
◽
Keyword(s):
Vlsi Design
◽
Network On Chip
◽
Energy Modeling
◽
Low Energy
◽
On Chip
Download Full-text
Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip
JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY
◽
10.3724/sp.j.1146.2012.00654
◽
2014
◽
Vol 35
(2)
◽
pp. 341-346
Author(s):
Xiao-fu Zheng
◽
Hua-xi Gu
◽
Yin-tang Yang
◽
Zhong-fan Huang
Keyword(s):
Network On Chip
◽
Low Latency
◽
Router Architecture
◽
On Chip
Download Full-text
Example Antenna and Link Performance for Wireless Network on Chip Applications
12th European Conference on Antennas and Propagation (EuCAP 2018)
◽
10.1049/cp.2018.0956
◽
2018
◽
Author(s):
W. Rayess
◽
D.W. Matolak
Keyword(s):
Wireless Network
◽
Network On Chip
◽
Link Performance
◽
On Chip
Download Full-text
An optimized path-setup method for mesh based Optical Network on Chip
2015 14th International Conference on Optical Communications and Networks (ICOCN)
◽
10.1109/icocn.2015.7203619
◽
2015
◽
Author(s):
Wei Tan
◽
Bowen Zhang
◽
Huaxi Gu
◽
Zheng Chen
Keyword(s):
Optical Network
◽
Network On Chip
◽
On Chip
Download Full-text
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