An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

2007 ◽  
Vol 51 (3) ◽  
pp. 245-256 ◽  
Author(s):  
Shuenn-Shyang Wang ◽  
Chien-Sung Li
Micromachines ◽  
2019 ◽  
Vol 10 (8) ◽  
pp. 509 ◽  
Author(s):  
Hasan Erdem Yantır ◽  
Wenzhe Guo ◽  
Ahmed M. Eltawil ◽  
Fadi J. Kurdahi ◽  
Khaled Nabil Salama

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.


Author(s):  
J.A. Hidalgo ◽  
J. Lopez ◽  
F. Arguello ◽  
E.L. Zapata

Sign in / Sign up

Export Citation Format

Share Document