scholarly journals An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

Micromachines ◽  
2019 ◽  
Vol 10 (8) ◽  
pp. 509 ◽  
Author(s):  
Hasan Erdem Yantır ◽  
Wenzhe Guo ◽  
Ahmed M. Eltawil ◽  
Fadi J. Kurdahi ◽  
Khaled Nabil Salama
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Current Literature ◽  
Power Efficiency ◽  
Design Principles ◽  
The Other ◽  
Area Efficiency ◽  
Processor Architectures ◽  
Fft Processor ◽  
Area Efficient

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.

scholarly journals Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

2021 ◽  
Vol 16 (2) ◽  
pp. 1-11
Author(s):  
André Sapper ◽  
Guilherme Paim ◽  
Eduardo Antônio César Da Costa ◽  
Sergio Bampi
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Power Efficiency ◽  
Cordic Algorithm ◽  
Standard Cell ◽  
Clock Gating ◽  
Power Efficient ◽  
Coordinate Rotation ◽  
Hardware Architectures ◽  
Point Fast Fourier Transform

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

scholarly journals FFT-ASSISTED ALGORITHMS FOR 3D LINE-CONTACT PROBLEMS

2021 ◽  
Vol 13 (2) ◽  
pp. 124-129
Author(s):  
Sergiu Spinu ◽  
◽  
Keyword(s):  
Fourier Transform ◽  
Contact Problem ◽  
Fast Fourier Transform ◽  
Contact Area ◽  
Contact Problems ◽  
Contact Length ◽  
The Other ◽  
Line Contact ◽  
Contact Width ◽  
Length Direction

The line-contact is a particular type of contact with a contact length much greater than its width. Such contact scenarios can be treated in the frame of a two-dimensional plane-strain problem if the contacting surfaces can be considered nominally smooth. However, surface irregularities inherent to any manufacturing technique lead to a discontinuous contact area that differs from the one derived on the basis of the smooth profile assumption. It is therefore tantalizing to pursue the solution of a line-contact problem using an intrinsically three-dimensional (3D) model, which can only be numerical due to lack of general analytical solutions in contact mechanics. Considering the geometry of the line-contact, a major challenge in its numerical modelling is that the expected contact area is orders of magnitude larger in one direction compared to the other. This may lead to an unreasonably large number of grids in the contact length direction, which translates to a prohibitive computational burden. An alternative approach, employed in this paper, is to treat the line-contact as non-periodic in the contact width direction, but periodic in the contact length direction, with a period equal to the window required to capture and replicate the surface specific texture. This periodicity encourages the contact problem solution by spectral methods based on the fast Fourier transform (FFT) algorithm. Based on this idea, two methods are derived in this paper from the existing Discrete Convolution Fast Fourier Transform (DCFFT) technique, which was previously developed for purely non-periodic contact problems. A first algorithm variant employs a special padding technique for pressure, whereas a second one mimics the contribution of multiple pressure periods by summation of the influence coefficients over a domain a few times larger than the target domain. Both techniques are validated against the existing analytical Hertz solution for the line-contact and a good agreement is found. The advanced methods seem well adapted to the simulation of contact problems that can be approximated as periodic in one direction and non-periodic in the other.

scholarly journals Simulation of Memory-Based 1024-Point Fast Fourier Transform for Broadband Wireless Access Technology on FPGA

2017 ◽  
Vol 1 (02) ◽  
pp. 28-36 ◽  
Author(s):  
Dinda Pramanta ◽  
Denny Darlis ◽  
Iswahyudi Hidayat
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Power Efficiency ◽  
Orthogonal Frequency Division Multiplexing ◽  
Wireless Access ◽  
Computational Time ◽  
Broadband Wireless Access ◽  
Access Technology ◽  
Broadband Wireless ◽  
Flip Flop

The limited radio frequency spectrum that can be used for transmission leads to bandwidth and power efficiency being a key requirement in the development of wireless access technology from 3G to 5G today. Data communication technology also requires this as mentioned on high speed network standards such as DSL, WLAN and WMAN with its products ADSL, WiFi and Wimax. In the last few decades we have seen the evolution of the Orthogonal Frequency Division Multiplexing (OFDM) modulation technique used in the technologies mentioned earlier to this day. This technique is regarded as a standard technology for broadband wireless access technology. In hardware implementation, the most preferred by many researchers is the Field Programmable Gate Array chip, as it can be reconfigured. The OFDM technique can be easily implemented because it uses Fast Fourier Transform (FFT) algorithms that are coding and programming capable of reducing the computational time of Discrete Fourier Transform. This paper discusses the implementation of the memory-based 1024-point IFFT / FFT for BWA communications. The design is focused on synthesizing and implementing the system block FFT 1024-point radix-4 using Decimation in Frequency (DIF) method. Implementation for IFFT / FFT 1024-point resource usage slice number 1%, the number of slice flip-flop 1%, the number 4 LUT (Look Up Table) 1%, and the number of IOB 27%. of the FPGA are used.

scholarly journals Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-13 ◽  
Author(s):  
Marwan A. Jaber ◽  
Daniel Massicotte
Keyword(s):  
Fourier Transform ◽  
Parallel Processing ◽  
Fast Fourier Transform ◽  
Critical Path ◽  
Building Blocks ◽  
Circuit Diagram ◽  
Fft Processor ◽  
Building Process ◽  
Complex Multiplier

This paper describes an embedded FFT processor where the higher radices butterflies maintain one complex multiplier in its critical path. Based on the concept of a radix-r fast Fourier factorization and based on the FFT parallel processing, we introduce a new concept of a radix-r Fast Fourier Transform in which the concept of the radix-r butterfly computation has been formulated as the combination of radix-2α/4β butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices would be feasible since it maintains approximately the same complexity of the radix-2/4 butterfly which is obtained by block building of the radix-2/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2/4 module that is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2/4 module.

scholarly journals Double Precision Floating Point Fft Processor using Vedic Mathematics

2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Vedic Mathematics ◽  
Communication Signal ◽  
Fft Processor ◽  
Complex Multiplications ◽  
Point Fast Fourier Transform

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

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