Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation

Journal of Signal Processing Systems ◽

10.1007/s11265-021-01680-0 ◽

2021 ◽

Author(s):

Saleh Usman ◽

Mohammad M. Mansour

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Decoding Algorithm ◽

Ldpc Decoding

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Improved Method for LDPC Decoding Algorithm Aided by Segmented Cyclic Redundancy Checks

JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY ◽

10.3724/sp.j.1146.2006.01763 ◽

2011 ◽

Vol 30 (5) ◽

pp. 1167-1170

Author(s):

Wei-hua Li ◽

Bing-li Jiao

Keyword(s):

Improved Method ◽

Decoding Algorithm ◽

Ldpc Decoding

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

Area Efficient

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An Improved Offset Min-Sum LDPC Decoding Algorithm for 5G New Radio

2021 International Symposium on Electrical and Electronics Engineering (ISEE) ◽

10.1109/isee51682.2021.9418782 ◽

2021 ◽

Author(s):

Bich Ngoc Tran-Thi ◽

Thien Truong Nguyen-Ly ◽

Hoa Nguyen Hong ◽

Trang Hoang

Keyword(s):

Decoding Algorithm ◽

Ldpc Decoding ◽

New Radio

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Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

2004 IEEE International Conference on Acoustics, Speech, and Signal Processing ◽

10.1109/icassp.2004.1327056 ◽

2004 ◽

Author(s):

Yongtao Wang ◽

H. Mahmoodi ◽

Lih-Yih Chiou ◽

Hunsoo Choo ◽

Jongsun Park ◽

...

Keyword(s):

Low Power ◽

Adaptive Filtering ◽

High Performance ◽

Hardware Architecture ◽

Vlsi Implementation ◽

Polyphase Channelizer

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A low-power, hard-decision analogue convolutional decoder using the modified feedback decoding algorithm

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328970 ◽

2004 ◽

Cited By ~ 2

Author(s):

B. Tomatsopoulos ◽

A. Demosthenous

Keyword(s):

Low Power ◽

Decoding Algorithm ◽

Hard Decision

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VLSI Implementation of Low-Power and High-SFDR Digital Frequency Synthesizer for Underwater Instruments and Network Systems

Springer Proceedings in Physics - Advanced Materials ◽

10.1007/978-3-319-03749-3_23 ◽

2014 ◽

pp. 289-304

Author(s):

Ying-Shen Juang ◽

Tze-Yun Sung ◽

Hsi-Chin Hsin

Keyword(s):

Low Power ◽

Frequency Synthesizer ◽

Vlsi Implementation ◽

Network Systems ◽

Digital Frequency

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Asynchronous low power VLSI implementation of the International Data Encryption Algorithm

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) ◽

10.1109/icecs.2001.957482 ◽

2002 ◽

Cited By ~ 3

Author(s):

N. Sklavos ◽

O. Koufopavlou

Keyword(s):

Low Power ◽

Data Encryption ◽

Vlsi Implementation ◽

Encryption Algorithm ◽

International Data

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A VLSI Implementation of Low Power, Low Data Rate UWB Transceiver for Location and Tracking Applications

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1007/s11265-006-7279-x ◽

2006 ◽

Vol 43 (1) ◽

pp. 43-58 ◽

Cited By ~ 6

Author(s):

Sakari Tiuraniemi ◽

Lucian Stoica ◽

Alberto Rabbachin ◽

Ian Oppermann

Keyword(s):

Low Power ◽

Data Rate ◽

Vlsi Implementation

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VLSI implementation of a low-power antilogarithmic converter

IEEE Transactions on Computers ◽

10.1109/tc.2003.1228517 ◽

2003 ◽

Vol 52 (9) ◽

pp. 1221-1228 ◽

Cited By ~ 44

Author(s):

K.H. Abed ◽

R.E. Siferd

Keyword(s):

Low Power ◽

Vlsi Implementation

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A Low Complexity Model-Driven Deep Learning LDPC Decoding Algorithm

2021 IEEE 6th International Conference on Computer and Communication Systems (ICCCS) ◽

10.1109/icccs52626.2021.9449266 ◽

2021 ◽

Author(s):

Qingle WU ◽

Su-Kit TANG ◽

Yuanhui LIANG ◽

Chan Tong LAM ◽

Yan MA

Keyword(s):

Deep Learning ◽

Low Complexity ◽

Decoding Algorithm ◽

Model Driven ◽

Ldpc Decoding

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