High-Performance Eight-Channel Photonic Crystal Ring Resonator–Based Optical Demultiplexer for DWDM Applications

Plasmonics ◽  
2021 ◽  
Author(s):  
Anushka Berry ◽  
Nidhi Anand ◽  
Sangeetha Anandan ◽  
Prabu Krishnan
2018 ◽  
Vol 0 (0) ◽  
Author(s):  
S. Naghizade ◽  
S. M. Sattari-Esfahlan

AbstractHere, we proposed a high performance 16-channel optical demultiplexer using two-dimensional photonic crystal ring resonator for telecommunication systems. By plane wave expansion (PWE) method the photonic band gap (PBG) of proposed structure calculated. Then, with finite difference time domain (FDTD) method the performance parameters of designed two-dimensional photonic crystal demultiplexer are analyzed. It is found that the channel wavelength of wavelength-division multiplexing (WDM) is truly tuned by changing the structure parameters of the demultiplexer and position of rod. Output peaks located in the optical communication C-band and L-band with the transmission efficiency of 99 %. The demultiplexer exhibits high-quality factor of 5176, and spectral width of 0.3. Very low crosstalk values are between −19 dB and −90 dB where, device only occupies an area of 1708.65 µm2. The proposed compact 16-channel demultiplexer can find more applications for the ultra-compact WDM systems in highly integrated telecommunication circuits.


2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Hassan Mamnoon-Sofiani ◽  
Sahel Javahernia

Abstract All optical logic gates are building blocks for all optical data processors. One way of designing optical logic gates is using threshold switching which can be realized by combining an optical resonator with nonlinear Kerr effect. In this paper we showed that a novel structure consisting of nonlinear photonic crystal ring resonator which can be used for realizing optical NAND/NOR and majority gates. The delay time of the proposed NAND/NOR and majority gates are 2.5 ps and 1.5 ps respectively. Finite difference time domain and plane wave expansion methods were used for simulating the proposed optical logic gates. The total footprint of the proposed structure is about 988 μm2.


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