Novel fairness-aware co-scheduling for shared cache contention game on chip multiprocessors

2020 ◽  
Vol 526 ◽  
pp. 68-85
Author(s):  
Zheng Xiao ◽  
Liwen Chen ◽  
Bangyong Wang ◽  
Jiayi Du ◽  
Keqin Li
Keyword(s):  
Chip Multiprocessors ◽  
Shared Cache ◽  
Cache Contention ◽  
On Chip

Embedded RAIDs-on-chip for bus-based chip-multiprocessors

2014 ◽  
Vol 13 (4) ◽  
pp. 1-36 ◽  
Author(s):  
Luis Angel D. Bathen ◽  
Nikil D. Dutt
Keyword(s):  
Chip Multiprocessors ◽  
On Chip

A case for shared instruction cache on chip multiprocessors running OLTP

2004 ◽  
Vol 32 (3) ◽  
pp. 11-18 ◽  
Author(s):  
Partha Kundu ◽  
Murali Annavaram ◽  
Trung Diep ◽  
John Shen
Keyword(s):  
Chip Multiprocessors ◽  
Instruction Cache ◽  
On Chip

scholarly journals Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance

2012 ◽  
Vol 58 (1) ◽  
pp. 9-14 ◽  
Author(s):  
Dawid Zydek ◽  
Grzegorz Chmaj ◽  
Alaa Shawky ◽  
Henry Selvaraj
Keyword(s):  
High Performance ◽  
Chip Multiprocessors ◽  
Energy Savings ◽  
Processor Allocation ◽  
Processing Elements ◽  
Energy Models ◽  
Allocation Process ◽  
On Chip ◽  
Job Scheduler ◽  
Performance Computing

Location of Processor Allocator and Job Scheduler and Its Impact on CMP PerformanceHigh Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.

A High-Performance and Low-Power On-Chip Network with Reconfigurable Topology

2010 ◽  
pp. 309-329
Author(s):  
Mehdi Modarressi ◽  
Hamid Sarbazi-Azad
Keyword(s):  
High Performance ◽  
Chip Multiprocessors ◽  
Optimization Methods ◽  
Critical Feature ◽  
Design Constraints ◽  
Core System ◽  
Traffic Pattern ◽  
On Chip ◽  
Network Mapping ◽  
Application Specific

In this chapter, we present a reconfigurable architecture for network-on-chips (NoC) on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications, aiming to address one of the main drawbacks of existing application-specific NoC optimization methods, i.e. optimizing NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC as several different applications are integrated into the modern and complex multi-core system-on-chips and chip multiprocessors and an NoC that is designed to run exactly one application does not necessarily meet the design constraints of other applications. The proposed NoC supports multiple applications by configuring as a topology which matches the traffic pattern of the currently running application in the best way. In this chapter, we first introduce the proposed reconfigurable topology and then address the two problems of core to network mapping and topology exploration. Experimental results show that this architecture effectively improves the performance of NoCs and reduces power consumption.

Performance of On-Chip Multiprocessors for Vision Tasks (Summary)

2000 ◽  
pp. 242-249 ◽  
Author(s):  
Y. Chung ◽  
K. Park ◽  
W. Hahn ◽  
N. Park ◽  
V. K. Prasanna
Keyword(s):  
Chip Multiprocessors ◽  
On Chip
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