A High-Performance and Low-Power On-Chip Network with Reconfigurable Topology

In this chapter, we present a reconfigurable architecture for network-on-chips (NoC) on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications, aiming to address one of the main drawbacks of existing application-specific NoC optimization methods, i.e. optimizing NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC as several different applications are integrated into the modern and complex multi-core system-on-chips and chip multiprocessors and an NoC that is designed to run exactly one application does not necessarily meet the design constraints of other applications. The proposed NoC supports multiple applications by configuring as a topology which matches the traffic pattern of the currently running application in the best way. In this chapter, we first introduce the proposed reconfigurable topology and then address the two problems of core to network mapping and topology exploration. Experimental results show that this architecture effectively improves the performance of NoCs and reduces power consumption.

Dynamic Reconfigurable NoCs

The aim of this chapter is the definition of the main issues that arise when dealing with the design of a NoC-based reconfigurable system. In particular, after the definition of the target architecture, several factors, requirements and constraints that have to be taken into account during the design of reconfigurable NoCs will be described and analyzed. The second part of this chapter will focus on the main issues in dynamic reconfigurable NoCs design, such as the definition of a layered approach, of a packet-switched communication infrastructure, of a proper routing mechanism and of a communication protocol support. Finally, the last part of this chapter will deal with the description of the most relevant implementation details, such as the placement of the bus-macros, the design of the network switches and the physical implementation of the routing mechanism.

From MARTE to Reconfigurable NoCs

Due to the continuous exponential rise in SoC’s design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this chapter, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis.

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

High-Level Programming of Dynamically Reconfigurable NoC-Based Heterogeneous Multicore SoCs

With the increase in System-on-Chip (SoC) complexity and CMOS technology capabilities, the SoC design community has recently observed a convergence of a number of critical trends, all of them aimed at addressing the design gap: the advent of heterogeneous multicore SoCs and Networks-on-Chip and the recognition of the need for design reuse through Intellectual Property (IP) cores, for dynamic reconfigurability and for high abstraction-level design. In this chapter, we present a solution for High-level Programming of Dynamically Reconfigurable NoC-based Heterogeneous Multicore SoCs. Our solution, the Gannet framework, allows IP core-based Heterogeneous Multicore SoCs to be programmed using a high-level language whilst preserving the full potential for parallelism and dynamic reconfigurability inherent in such a system. The required hardware infrastructure is small and low-latency, thus adding full dynamic reconfiguration capabilities with a small overhead both in area and performance.

Reliability Aware Performance and Power Optimization in DVFS-Based On-Chip Networks

Recently, chip multi-processors (CMP) have emerged to fully utilize the increased transistor count within stringent power budgets. Transistor scaling has lead to more error-prone and defective components. Static and run-time induced variations in the circuit lead to reduced yield and reliability. Providing reliability at low overheads specifically in terms of power is a challenging task that requires innovative solutions for building future integrated chips. Static variations have been studied previously. In this proposal, we study the impact of run-time variations on reliability. On-chip interconnection network that forms the communication fabric in the CMP has a crucial role in determining the performance, power consumption and reliability of the system. We manage protecting the data in a network on chip from transient errors induced by voltage fluctuations. Variations in operating conditions result in a significant variation in the reliability of the system, motivating the need to provide tunable levels of data protection. For example, the use of Dynamic Voltage and Frequency Scaling (DVFS) technique used in most CMPs today results in voltage variation across the chip, giving rise to variable error rates across the chip. We investigated the design of a dynamically reconfigurable error protection scheme in a NoC to achieve a desired level of reliability. We protect data at the desired reliability while minimizing the power and performance overhead incurred. We obtain a maximum of 55% savings in the power expended for error protection in the network with our proposed reconfigurable ECC while maintaining constant reliability. Further, 35% reduction in the average message latency in the network is observed, making a case for providing tunability in error protection in the on-chip network fabric.

An Efficient Hardware/Software Communication Mechanism for Reconfigurable NoC

With the progress of technology, more and more intellectual properties (IPs) can be integrated into one single chip. The performance bottleneck has shifted from the computation in individual IPs to the communication among IPs. A Network-on-Chip (NoC) was proposed to provide high scalability and parallel communication. An ASIC-implemented NoC lacks flexibility and has a high non-recurring engineering (NRE) cost. As an alternative, we can implement an NoC in a Field Programmable Gate Arrays (FPGA). In addition, FPGA devices can support dynamic partial reconfiguration such that the hardware circuits can be configured into an FPGA at run time when necessary, without interfering hardware circuits that are already running. Such an FPGA-based NoC, namely reconfigurable NoC (RNoC), is more flexible and the NRE cost of FPGA-based NoC is also much lower than that of an ASIC-based NoC. Because of dynamic partial reconfiguration, there are several issues in the RNoC design. We focus on how communication between hardware and software can be made efficient for RNoC. We implement three communication architectures for RNoC namely single output FIFO-based architecture, multiple output FIFO-based architecture, and shared memory-based architecture. The average communication memory overhead is less on the single output FIFO-based architecture and the shared memory-based architecture than on the multiple output FIFO-based architecture when the lifetime interval is smaller than 0.5. In the performance analysis, some real applications are applied. Real application examples show that performance of the multiple output FIFO-based architecture is more efficient by as much as 1.789 times than the performance of the single output FIFO-based architecture. The performance of the shared memory-based architecture is more efficient by as much as 1.748 times than the performance of the single output FIFO-based architecture.

Keys for Administration of Reconfigurable NoC

This chapter presents an analysis of current needs in the domain of Reconfigurable Network on chip. We first detail our motivations for NoC reconfiguration, which is followed by a description of our model for Reconfigurable Network on chip in relation with the usual OSI network layers. Then, we propose a study of outstanding research issues of current work and open issues organized into three topics: dynamic reconfiguration administration, network infrastructure reconfiguration and network protocol reconfiguration. To finish, we present our strategy for reconfiguration and introduce a self-adaptive Network Interface architecture as a part of the configuration manager.

Dynamically Reconfigurable NoC for Future Heterogeneous Multi-core Architectures

To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard. This makes drNoC a highly re-useable communication framework, qualifying it as a communication centric platform for high data intensive SoC architectures. Simulation results show a 32% increase in data throughput and 22-35% decrease in network delay when compared with a traditional NoC with fixed parameters.

Design Methodologies and Mapping Algorithms for Reconfigurable NoC-Based Systems

This chapter describes in details the different approaches and design methodologies that can be employed in order to create reconfigurable Network-on-Chip-based systems. The target architecture can be mainly defined either as a homogeneous or as a non-homogeneous grid of tiles. Furthermore, in addition to these architectures, it is also possible to identify a regular non-homogeneous solution, which is a sort of mix of the previous two. A second distinction can be done based on the reconfiguration capabilities that the target system can support. In particular, by using one of the previously introduced architectures, it is possible to develop a reconfigurable system, based on the NoC paradigm, in which the communication infrastructure, the mapping of the computational cores or both can be dynamically configured at run-time.