Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

2017 ◽  
Vol 102 ◽  
pp. 175-185 ◽  
Author(s):  
Sayed T. Muhammad ◽  
Magdy A. El-Moursy ◽  
Ali A. El-Moursy ◽  
Hesham F.A. Hamed
Keyword(s):  
Process Variation ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip ◽  
Level Analysis

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip

2007 ◽  
Author(s):  
Xuan-Tu Tran ◽  
Jean Durupt ◽  
Yvain Thonnart ◽  
Francois Bertrand ◽  
Vincent Beroulle ◽  
...  
Keyword(s):  
Design For Test ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip ◽  
Test Architecture

Analysis and Design of Networks-on-Chip Under High Process Variation

2015 ◽  
Author(s):  
Rabab Ezz-Eldin ◽  
Magdy Ali El-Moursy ◽  
Hesham F. A. Hamed
Keyword(s):  
Process Variation ◽  
Networks On Chip ◽  
Analysis And Design ◽  
On Chip

Design-for-Test of Asynchronous Networks-on-Chip

2006 ◽  
Author(s):  
Xuan-Tu Tran ◽  
V. Beroulle ◽  
J. Durupt ◽  
C. Robach ◽  
F. Bertrand
Keyword(s):  
Design For Test ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip

scholarly journals A DFT Architecture for Asynchronous Networks-on-Chip

2006 ◽  
Author(s):  
Xuan-Tu Tran ◽  
J. Durupt ◽  
F. Bertrand ◽  
V. Beroulle ◽  
C. Robach
Keyword(s):  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip
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