Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip

2007 ◽  
Author(s):  
Xuan-Tu Tran ◽  
Jean Durupt ◽  
Yvain Thonnart ◽  
Francois Bertrand ◽  
Vincent Beroulle ◽  
...  
Keyword(s):  
Design For Test ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip ◽  
Test Architecture

Design-for-Test of Asynchronous Networks-on-Chip

2006 ◽  
Author(s):  
Xuan-Tu Tran ◽  
V. Beroulle ◽  
J. Durupt ◽  
C. Robach ◽  
F. Bertrand
Keyword(s):  
Design For Test ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip

Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

2017 ◽  
Vol 102 ◽  
pp. 175-185 ◽  
Author(s):  
Sayed T. Muhammad ◽  
Magdy A. El-Moursy ◽  
Ali A. El-Moursy ◽  
Hesham F.A. Hamed
Keyword(s):  
Process Variation ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip ◽  
Level Analysis

Efficient Design-for-Test Approach for Networks-on-Chip

2018 ◽  
pp. 1-1 ◽  
Author(s):  
Junshi Wang ◽  
Masoumeh Ebrahimi ◽  
Letian Huang ◽  
Xuan Xie ◽  
Qiang Li ◽  
...  
Keyword(s):  
Design For Test ◽  
Efficient Design ◽  
Networks On Chip ◽  
On Chip

scholarly journals A DFT Architecture for Asynchronous Networks-on-Chip

2006 ◽  
Author(s):  
Xuan-Tu Tran ◽  
J. Durupt ◽  
F. Bertrand ◽  
V. Beroulle ◽  
C. Robach
Keyword(s):  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip
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