Fixed-point multiplication is an important operation that is frequently used in many digital signal processing (DSP) applications. The operation is computationally intense and very often the performance of multiplier determines the overall performance of DSP system. Evidently, a wide range of approaches have been proposed for efficient implementation of fixed-point multipliers on different hardware platforms. In this paper, we use Coordinate Rotation DIgital Computer (CORDIC) algorithm to perform fixed-point multiplication operation. The motivation for our approach is based on the fact that CORDIC is a hardware-efficient algorithm, wherein accuracy can be traded-off for performance. Our implementation targets field programmable gate arrays (FPGAs) and focuses on exploiting the underlying general and specialized fabric to the fullest. Performance comparisons against various traditional and recent approaches show that a substantial improvement is achievable by using CORDIC-based multipliers. We have also implemented a recently proposed convolution architecture using CORDIC-based multipliers. The results show that a proper choice of CORDIC architecture can result in an improvement of performance parameters like resource utilization, throughput and dynamic power. This, however, is achieved in lieu of a small cost in accuracy. Our analysis of an 8-stage CORDIC multiplier reports a mean absolute percentage error (MAPE) of 6.032 — a factor that reduces exponentially with increasing number of stages.
Hardware Architectures of the QR-Decomposition Based on a Givens Rotation Technique
