Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs

2008 ◽  
Vol 32 (5-6) ◽  
pp. 303-312 ◽  
Author(s):  
Andrzej Krasniewski
Keyword(s):  
Error Detection ◽  
Finite State Machines ◽  
Concurrent Error Detection ◽  
State Machines ◽  
Embedded Memory ◽  
Finite State

scholarly journals Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM

2007 ◽  
Vol 17 (4) ◽  
pp. 565-575 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Sławomir Chmielewski
Keyword(s):  
Finite State Machine ◽  
Finite State Machines ◽  
Optimization Methods ◽  
State Machine ◽  
Logic Circuits ◽  
State Machines ◽  
Embedded Memory ◽  
Effective Application ◽  
Finite State

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSMOptimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

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