A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA
2020 ◽
Vol 74
◽
pp. 103014
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1990 ◽
Vol 38
(8)
◽
pp. 1310-1313
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Keyword(s):
2005 ◽
Vol E88-C
(4)
◽
pp. 559-569
◽