An enhanced planned obsolescence attack by aging networks-on-chip

2021 ◽  
Vol 117 ◽  
pp. 102093
Author(s):  
Yinyuan Zhao ◽  
Xiaohang Wang ◽  
Yingtao Jiang ◽  
Liang Wang ◽  
Amit Kumar Singh ◽  
...  
Keyword(s):  
Planned Obsolescence ◽  
Networks On Chip ◽  
On Chip

Abetting Planned Obsolescence by Aging 3D Networks-on-Chip

2018 ◽  
Author(s):  
Sourav Das ◽  
Kanad Basu ◽  
Janardhan Rao Doppa ◽  
Partha Pratim Pande ◽  
Ramesh Karri ◽  
...  
Keyword(s):  
Planned Obsolescence ◽  
Networks On Chip ◽  
On Chip ◽  
3D Networks

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

Deadlock-Free Adaptive Routing in Networks -on-Chip Using Overlapping Virtual Networks

2021 ◽  
pp. 1-1
Author(s):  
Dong Xiang ◽  
Xiang Ji ◽  
Yuan Cai ◽  
Binzhang Fu
Keyword(s):  
Adaptive Routing ◽  
Virtual Networks ◽  
Networks On Chip ◽  
On Chip

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection

2021 ◽  
Author(s):  
Yu-Kai Chuang ◽  
Yong Zhong ◽  
Yi-Hao Cheng ◽  
Bo-Yi Yu ◽  
Shao-Yun Fang ◽  
...  
Keyword(s):  
Optical Networks ◽  
Fault Tolerant ◽  
Networks On Chip ◽  
On Chip

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA

2017 ◽  
Vol 10 (4) ◽  
pp. 1-27 ◽  
Author(s):  
Thiem Van Chu ◽  
Shimpei Sato ◽  
Kenji Kise
Keyword(s):  
Large Scale ◽  
Networks On Chip ◽  
On Chip ◽  
Large Scale Networks

Automated synthesis of custom networks-on-chip for real world applications

2020 ◽  
Author(s):  
Anup Gangwar ◽  
Nitin Kumar Agarwal ◽  
Ravishankar Sreedharan ◽  
Ambica Prasad ◽  
Sri Harsha Gade ◽  
...  
Keyword(s):  
Real World ◽  
Automated Synthesis ◽  
Networks On Chip ◽  
Real World Applications ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document