Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

Integration ◽  
2021 ◽  
Author(s):  
Nizar Dahir ◽  
Ammar Karkar ◽  
Maurizio Palesi ◽  
Terrence Mak ◽  
Alex Yakovlev
Keyword(s):  
Power Density ◽  
Network On Chip ◽  
Multi Objective ◽  
Application Mapping ◽  
On Chip

Unified multi‐objective mapping for network‐on‐chip using genetic‐based hyper‐heuristic algorithms

2018 ◽  
Vol 12 (4) ◽  
pp. 158-166 ◽  
Author(s):  
Changqing Xu ◽  
Yi Liu ◽  
Peng Li ◽  
YinTang Yang
Keyword(s):  
Heuristic Algorithms ◽  
Network On Chip ◽  
Multi Objective ◽  
On Chip

Optimal scheduling algorithms of system chip power density based on network on chip

2021 ◽  
pp. 120-127
Author(s):  
Jiashen Li ◽  
◽  
Yun Pan ◽  
Keyword(s):  
Dynamic Programming ◽  
Power Density ◽  
Simulated Annealing Algorithm ◽  
Dynamic Programming Algorithm ◽  
Network On Chip ◽  
Thermal Design ◽  
Optimal Scheduling ◽  
Programming Algorithm ◽  
System Throughput ◽  
On Chip

The improvement of chip integration leads to the increase of power density of system chips, which leads to the overheating of system chips. When dispatching the power density of system chips, some working modules are selectively closed to avoid all modules on the chip being turned on at the same time and to solve the problem of overheating. Taking 2D grid-on-chip network as the research object, an optimal scheduling algorithm of system-on-chip power density based on network-on-chip (NoC) is proposed. Under the constraints of thermal design power (TDP) and system, dynamic programming algorithm is used to solve the optimal application set throughput allocation from bottom to top by dynamic programming for the number and frequency level of each application configuration processor under the given application set of network-on-chip. On this basis, the simulated annealing algorithm is used to complete the application mapping aiming at heat dissipation effect and communication delay. The open and closed processor layout is determined. After obtaining the layout results, the TDP is adjusted. The maximum TDP constraint is iteratively searched according to the feedback loop of the system over-hot spots, and the power density scheduling performance of the system chip is maximized under this constraint, so as to ensure the system core. At the same time, chip throughput can effectively solve the problem of chip overheating. The experimental results show that the proposed algorithm increases the system chip throughput by about 11%, improves the system throughput loss, and achieves a balance between the system chip power consumption and scheduling time.

Application Mapping on Network-on-Chip

2018 ◽  
pp. 119-154
Author(s):  
Santanu Kundu ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Application Mapping ◽  
On Chip
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