The mesh network is an important topology for on-chip networks since it provides great flexibility for the on-chip interconnection with diverse application requirements. We have proposed the tree-based routing architecture for on-chip networks called TRAIN, which achieves deadlock freedom and high-performance communication for on-chip networks. With TRAIN, a packet arriving in a switch can be adaptively routed to utilize a shortcut to reduce the distance to the destination switch efficiently. In this paper, we propose two arbitration schemes in a TRAIN switch and their arbiter designs: the sequential arbiter and the shortcut-first arbiter. The experimental results show that the shortcut-first arbiter achieves better performance than the sequential arbiter, while the former costs larger chip area. With the network size grows, the performance advantage is more pronounced for the shortcut-first arbiter.
On-chip network design automation with source routing switches