scholarly journals A fixed-point implementation of tone mapping operation for HDR images expressed in floating-point format

2014 ◽  
Vol 3 ◽  
Author(s):  
Toshiyuki Dobashi ◽  
Atsushi Tashiro ◽  
Masahiro Iwahashi ◽  
Hitoshi Kiya
Keyword(s):  
Fixed Point ◽  
Dynamic Range ◽  
Floating Point ◽  
Tone Mapping ◽  
Fixed Point Arithmetic ◽  
Memory Cost ◽  
Point Data ◽  
Point Arithmetic ◽  
Intermediate Format ◽  
Hdr Image

A tone mapping operation (TMO) for HDR images with fixed-point arithmetic is proposed. A TMO generates a low dynamic range (LDR) image from a high dynamic range (HDR) image by compressing its dynamic range. Since HDR images are generally expressed in a floating-point data format, a TMO also deals with floating-point data even though resulting LDR images have integer data. As a result, conventional TMOs require many resources such as computational and memory cost. To reduce the resources, an integer TMO which treats a floating-point number as two 8-bit integer numbers was proposed. However, this method has the limitation of available input HDR image formats. The proposed method introduces an intermediate format to relieve the limitation of input formats, and expands the integer TMO for the intermediate format. The proposed integer TMO can be applied for multiple formats such as the RGBE and the OpenEXR. Moreover, the method can conduct all calculations in the TMO with fixed-point arithmetic. Using both integer data and fixed-point arithmetic, the method reduces not only the memory cost, but also the computational cost. The experimental and evaluation results show that the proposed method reduces the computational and memory cost, and gives almost same quality of LDR images, compared with the conventional method with floating-point arithmetic.

scholarly journals High-Level Synthesis under Fixed-Point Accuracy Constraint

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Daniel Menard ◽  
Nicolas Herve ◽  
Olivier Sentieys ◽  
Hai-Nam Nguyen
Keyword(s):  
Signal Processing ◽  
Fixed Point ◽  
Word Length ◽  
High Level Synthesis ◽  
Floating Point ◽  
Fixed Point Arithmetic ◽  
Resource Binding ◽  
High Level ◽  
Point Arithmetic ◽  
Length Optimization

Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%.

scholarly journals Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ordinary differential equations

2020 ◽  
Vol 378 (2166) ◽  
pp. 20190052 ◽  
Author(s):  
Michael Hopkins ◽  
Mantas Mikaitis ◽  
Dave R. Lester ◽  
Steve Furber
Keyword(s):  
Fixed Point ◽  
Differential Equations ◽  
Ordinary Differential Equations ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Least Significant Bit ◽  
Fixed Point Arithmetic ◽  
Solution Algorithms ◽  
Point Arithmetic

Although double-precision floating-point arithmetic currently dominates high-performance computing, there is increasing interest in smaller and simpler arithmetic types. The main reasons are potential improvements in energy efficiency and memory footprint and bandwidth. However, simply switching to lower-precision types typically results in increased numerical errors. We investigate approaches to improving the accuracy of reduced-precision fixed-point arithmetic types, using examples in an important domain for numerical computation in neuroscience: the solution of ordinary differential equations (ODEs). The Izhikevich neuron model is used to demonstrate that rounding has an important role in producing accurate spike timings from explicit ODE solution algorithms. In particular, fixed-point arithmetic with stochastic rounding consistently results in smaller errors compared to single-precision floating-point and fixed-point arithmetic with round-to-nearest across a range of neuron behaviours and ODE solvers. A computationally much cheaper alternative is also investigated, inspired by the concept of dither that is a widely understood mechanism for providing resolution below the least significant bit in digital signal processing. These results will have implications for the solution of ODEs in other subject areas, and should also be directly relevant to the huge range of practical problems that are represented by partial differential equations. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.

Fixed point versus floating point

SIMULATION ◽  
1968 ◽  
Vol 11 (1) ◽  
pp. 13-15
Author(s):  
Leonard H. Teitelbaum
Keyword(s):  
Fixed Point ◽  
Computer Time ◽  
Simulation System ◽  
Floating Point ◽  
Digital To Analog Converter ◽  
Floating Point Arithmetic ◽  
Fixed Point Arithmetic ◽  
Analog Converter ◽  
Point Versus ◽  
Point Arithmetic

This paper discusses the advantages of using fixed-point arithmetic in a hybrid environment. The particular ex ample used is that of a hybrid simulation system. The paper discusses the performance penalties which are paid in using floating-point arithmetic as opposed to fixed-point arithmetic. The paper points out the amount of digital- computer time used in fixed-point to floating-point con version. It also suggests a new hardware device, a floating point/fixed-point digital-to-analog converter. This paper points out one application in which this device could be useful.

The Effects of Precision Constraints in a Backpropagation Learning Network

1990 ◽  
Vol 2 (3) ◽  
pp. 363-373 ◽  
Author(s):  
Paul W. Hollis ◽  
John S. Harper ◽  
John J. Paulos
Keyword(s):  
Fixed Point ◽  
Analog Circuits ◽  
Learning System ◽  
Backpropagation Algorithm ◽  
Learning Network ◽  
Fixed Point Arithmetic ◽  
Point Arithmetic ◽  
Backpropagation Learning

This paper presents a study of precision constraints imposed by a hybrid chip architecture with analog neurons and digital backpropagation calculations. Conversions between the analog and digital domains and weight storage restrictions impose precision limits on both analog and digital calculations. It is shown through simulations that a learning system of this nature can be implemented in spite of limited resolution in the analog circuits and using fixed point arithmetic to implement the backpropagation algorithm.

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