MLoF: Machine Learning Accelerators for the Low-Cost FPGA Platforms

In Internet of Things (IoT) scenarios, it is challenging to deploy Machine Learning (ML) algorithms on low-cost Field Programmable Gate Arrays (FPGAs) in a real-time, cost-efficient, and high-performance way. This paper introduces Machine Learning on FPGA (MLoF), a series of ML IP cores implemented on the low-cost FPGA platforms, aiming at helping more IoT developers to achieve comprehensive performance in various tasks. With Verilog, we deploy and accelerate Artificial Neural Networks (ANNs), Decision Trees (DTs), K-Nearest Neighbors (k-NNs), and Support Vector Machines (SVMs) on 10 different FPGA development boards from seven producers. Additionally, we analyze and evaluate our design with six datasets, and compare the best-performing FPGAs with traditional SoC-based systems including NVIDIA Jetson Nano, Raspberry Pi 3B+, and STM32L476 Nucle. The results show that Lattice’s ICE40UP5 achieves the best overall performance with low power consumption, on which MLoF averagely reduces power by 891% and increases performance by 9 times. Moreover, its cost, power, Latency Production (CPLP) outperforms SoC-based systems by 25 times, which demonstrates the significance of MLoF in endpoint deployment of ML algorithms. Furthermore, we make all of the code open-source in order to promote future research.

Computing a Group of Polynomials over a Galois Field in FPGA Architecture

For the most extensive range of tasks, such as real-time data processing in intelligent transport systems, etc., advanced computer-based techniques are required. They include field-programmable gate arrays (FPGAs). This paper proposes a method of pre-calculating the hardware complexity of computing a group of polynomial functions depending on the number of input variables of the said functions, based on the microchips of FPGAs. These assessments are reduced for a group of polynomial functions due to computing the common values of elementary polynomials. Implementation is performed using similar software IP-cores adapted to the architecture of user-programmable logic arrays. The architecture of FPGAs includes lookup tables and D flip-flops. This circumstance ensures that the pipelined data processing provides the highest operating speed of a device, which implements the group of polynomial functions defined over a Galois field, independently of the number of variables of the said functions. A group of polynomial functions is computed based on common variables. Therefore, the input/output blocks of FPGAs are not a significant limiting factor for the hardware complexity estimates. Estimates obtained in using the method proposed allow evaluating the amount of the reconfigurable resources of FPGAs, required for implementing a group of polynomial functions defined over a Galois field. This refers to both the existing FPGAs and promising ones that have not yet been implemented.

Automatic FPGA Placement Configuration for Customer Designs

Searching for new ways to improve the efficiency of integrated circuits (IC) led to the development of specialized heterogeneous configurable IC (FPGA) and systems-on-a-chip. Their key feature is an extended interpretation of standard cell library, containing ready-to-use IP cores along with standard cells. Specific customer designs require the flexibility of the configurable heterogeneous IC’s architecture and, therefore, automatic CAD clustering and placement algorithms configuration. The development of efficient configuration methods and algorithms is impossible without relying on the mathematical apparatus. In this work, such mathematical apparatus is provided. The authors described a set-theoretic model of a hierarchical project and formalized the hierarchical approach to the netlist, using the apparatus of mathematical logic, set and graph theories. The correspondence between the customers designs’ elements and FPGA’s elements has been formalized to provide fast clustering and placement configuration. The obtained results provide the basis for future efficient methods for automatic placement and clustering configuration.

3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

Power optimization is an important part of network-on-chip(NoC) design. This paper proposes an improved algorithm based on genetic algorithm on how to properly map IP (Intellectual Property) cores to 3D NoC. First, in view of the randomness of the traditional genetic algorithm in individual selection, an improved greedy algorithm is used in the initial population generation stage to make the generated individuals reach the optimal. Secondly, in view of the weak local optimization ability of the traditional genetic algorithm and prone to premature problems, the simulated annealing algorithm is added in the crossover operation stage to make the offspring reach the global optimum. The experimental results show that compared with the traditional genetic algorithm, the algorithm has better convergence and low power consumption performance, which can quickly search for a better solution, in the case of a large number of cores (124 IP cores), the average power consumption can be reduced by 42.2%.