Unified array architecture for discrete cosine transform, sine transform and their inverses

1995 ◽  
Vol 31 (21) ◽  
pp. 1811-1812 ◽  
Author(s):  
Jiun-In Guo ◽  
Chein-Wei Jen ◽  
Chingson Chen
Keyword(s):  
Discrete Cosine Transform ◽  
Cosine Transform ◽  
Sine Transform ◽  
Array Architecture

scholarly journals Improved Algorithm for ODCT Computation of a Running Data Sequence

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
S. Akhter ◽  
V. Karwal ◽  
R. C. Jain
Keyword(s):  
Real Time ◽  
Discrete Cosine Transform ◽  
Input Data ◽  
Time Sequence ◽  
Data Sequence ◽  
Cosine Transform ◽  
Rectangular Window ◽  
Sine Transform ◽  
Data Points ◽  
Transform Coefficients

Fast windowed update algorithms capable of independently updating the odd discrete cosine transform (ODCT) and odd discrete sine transform (ODST) of a running data sequence are analytically developed. In this algorithm, to compute the ODCT coefficients of a real-time sequence, we do not require the ODST coefficients. Similarly, the ODST coefficients of the shifted sequence can be calculated without using ODCT coefficients. The running input data sequence is sampled using a rectangular window. However, this idea can be easily extended for other windows. The update algorithm derived herein can be used to compute the transform coefficients of the shifted sequence as new data points are available. The complexity of developed algorithm isO(N). The validity of algorithm is tested by MATLAB simulations.

scholarly journals A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure

2011 ◽  
Vol 1 (2) ◽  
Author(s):  
Doru Chiper
Keyword(s):  
Discrete Cosine Transform ◽  
Systolic Array ◽  
Correlation Structure ◽  
Efficient Design ◽  
Hardware Complexity ◽  
Cosine Transform ◽  
Type Iv ◽  
Vlsi Chip ◽  
Array Architecture ◽  
Vlsi Algorithm

AbstractA new VLSI algorithm and its associated systolic array architecture for a prime length type IV discrete cosine transform is presented. They represent the basis of an efficient design approach for deriving a linear systolic array architecture for type IV DCT. The proposed algorithm uses a regular computational structure called pseudoband correlation structure that is appropriate for a VLSI implementation. The proposed algorithm is then mapped onto a linear systolic array with a small number of I/O channels and low I/O bandwidth. The proposed architecture can be unified with that obtained for type IV DST due to a similar kernel. A highly efficient VLSI chip can be thus obtained with good performance in the architectural topology, computing parallelism, processing speed, hardware complexity and I/O costs similar to those obtained for circular correlation and cyclic convolution computational structures.

Multiplierless array architecture for computing Discrete Cosine Transform

1995 ◽  
Vol 21 (1) ◽  
pp. 13-19 ◽  
Author(s):  
Manik Chandra Mandal ◽  
Anindya Sundar Dhar ◽  
Swapna Banerjee
Keyword(s):  
Discrete Cosine Transform ◽  
Cosine Transform ◽  
Array Architecture
Sign in / Sign up

Export Citation Format

Share Document