Development of improved direct current based saturated core fault current limiter in DFIG system for enhancing the low voltage ride-through capability

2020 ◽  
Vol 14 (1) ◽  
pp. 148-156 ◽  
Author(s):  
Prashant Mani Tripathi ◽  
Kalyan Chatterjee
Keyword(s):  
Direct Current ◽  
Low Voltage ◽  
Fault Current ◽  
Fault Current Limiter ◽  
Low Voltage Ride Through ◽  
Current Limiter

scholarly journals Study on Operational Characteristics of Protection Relay with Fault Current Limiters in an LVDC System

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 322
Author(s):  
Hyeong-Jin Lee ◽  
Jin-Seok Kim ◽  
Jae-Chul Kim ◽  
Sang-Yun Yun ◽  
Sung-Min Cho
Keyword(s):  
Direct Current ◽  
Distribution System ◽  
Low Voltage ◽  
Current System ◽  
Fault Analysis ◽  
Fault Current ◽  
Fault Current Limiter ◽  
Superconducting Fault Current Limiter ◽  
Protection Relay ◽  
Current Limiter

As the application of low-voltage-direct-current system increases, fault analysis in the low-voltage-direct-current system has essential because the fault response has different from the conventional AC distribution system. Especially, the fault current by the discharge current of the capacitor in the low-voltage-direct-current distribution system has very large compared with the conventional AC distribution system. Therefore, this paper proposed the application of the superconducting fault current limiter for limiting the fault current on the low-voltage-direct-current system. As one of the protected methods against fault current, the superconducting fault current limiter which could quickly limit the fault current has been noticed as an attractive method. However, the protection relay may malfunction such as over current relay, selective protection relay due to limiting fault current by applying superconducting fault current limiter. Therefore, in this paper proposed a solution to malfunction problem of the protection relay using the voltage components of the high temperature superconductivity. This paper verified the effect of the proposed method through test modelling and PSCAD/EMTDC.

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