Design of a current-mode continuous-time Sigma-Delta modulator with exponential feedback for improved jitter rejection

2009 ◽  
Vol 96 (11) ◽  
pp. 1127-1144 ◽  
Author(s):  
L. Quintanilla ◽  
J. Arias ◽  
L. Enríquez ◽  
J. Vicente ◽  
J. Hernández ◽  
...  
2015 ◽  
Vol 63 (4) ◽  
pp. 919-922 ◽  
Author(s):  
P. Śniatała ◽  
M. Naumowicz ◽  
A. Handkiewicz ◽  
S. Szczęsny ◽  
J.L.A. de Melo ◽  
...  

Abstract The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.


Author(s):  
Chang-Joon Park ◽  
Hemasundar Mohan Geddada ◽  
Aydin Ilker Karsilayan ◽  
Jose Silva-Martinez ◽  
Marvin Onabajo

2007 ◽  
Vol 42 (12) ◽  
pp. 2696-2705 ◽  
Author(s):  
Lucien J. Breems ◽  
Robert Rutten ◽  
Robert H. M. van Veldhoven ◽  
Gerard van der Weide

2011 ◽  
Vol 02 (03) ◽  
pp. 201-209 ◽  
Author(s):  
Jhin-Fang Huang ◽  
Yan-Cheng Lai ◽  
Wen-Cheng Lai ◽  
Ron-Yi Liu

Sign in / Sign up

Export Citation Format

Share Document