ASYMPTOTIC ANALYSIS OF THE THERMAL STRESSES IN A TWO-LAYER COMPOSITE WITH AN ADHESIVE LAYER

1985 ◽  
Vol 8 (2) ◽  
pp. 183-203 ◽  
Author(s):  
Harry E. Williams
2021 ◽  
pp. 83-95
Author(s):  
Francesco Marchione

The adhesive technique is observing a considerable increase in applications in various fields. Unlike traditional joining methods, this technology allows the stress peaks and the weight of the resulting structure to be reduced. Adhesive joints during their service life not only undergo mechanical but also thermal stresses. The thermal compatibility between the adhesive and the adherents used is a fundamental aspect to consider in the design phase. This paper reports on and analyses the results obtained from a linear Finite Element Method (FEM) simulation for a hybrid adhesive joint, as the thickness and characteristics of the adhesive layer vary. An analytical solution for adhesive free joints is presented according to both beam and plate theories. The analytical and numerical results, in case of no adhesive, are in good agreement with good approximation. The introduction of the adhesive layer allows to obtain higher displacement values than in the adhesive-free configuration. The increase in displacement and therefore in ductility confirms the effectiveness of the adhesive joint for real applications.


1990 ◽  
Vol 112 (1) ◽  
pp. 77-80
Author(s):  
Agha J. Ghorieshi ◽  
Umid R. Nejib

Thermal stress management is a major factor in the design of an electronic package. Thermal mismatch among the assembled components induces thermal stresses within the device. Finite element technique is utilized for three dimensional thermal stress analysis of a transistor with a free convection cooling system. Heat transfer analysis is used to determine the temperature distribution throughout the package for a given operating temperature. The data are then used to determine package stresses. The results show the shear stress concentration is higher at the corner of the chip. These values were found to be lower compared to those using temperature cycle analysis. An alternative method of lowering shear stresses in the chip is suggested.


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