High Performance High-Precision Floating-Point Operations on FPGAs Using OpenCL

Author(s):  
Naohito Nakasato ◽  
Hiroshi Daisaka ◽  
Tadashi Ishikawa
Author(s):  
Jack Dongarra ◽  
Laura Grigori ◽  
Nicholas J. Higham

A number of features of today’s high-performance computers make it challenging to exploit these machines fully for computational science. These include increasing core counts but stagnant clock frequencies; the high cost of data movement; use of accelerators (GPUs, FPGAs, coprocessors), making architectures increasingly heterogeneous; and multi- ple precisions of floating-point arithmetic, including half-precision. Moreover, as well as maximizing speed and accuracy, minimizing energy consumption is an important criterion. New generations of algorithms are needed to tackle these challenges. We discuss some approaches that we can take to develop numerical algorithms for high-performance computational science, with a view to exploiting the next generation of supercomputers. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.


2013 ◽  
Vol 652-654 ◽  
pp. 2153-2158
Author(s):  
Wu Ji Jiang ◽  
Jing Wei

Controlling the tooth errors induced by the variation of diameter of grinding wheel is the key problem in the process of ZC1 worm grinding. In this paper, the influence of tooth errors by d1, m and z1 as the grinding wheel diameter changes are analyzed based on the mathematical model of the grinding process. A new mathematical model and truing principle for the grinding wheel of ZC1 worm is presented. The shape grinding wheel truing of ZC1 worm is carried out according to the model. The validity and feasibility of the mathematical model is proved by case studies. The mathematical model presented in this paper provides a new method for reducing the tooth errors of ZC1 worm and it can meet the high-performance and high-precision requirements of ZC1 worm grinding.


Author(s):  
Maura C. Kibbey ◽  
David MacAllan ◽  
James W. Karaszkiewicz

IGEN's ORIGEN® technology, which is based on electrochemiluminescence, has been adopted by a number of research and bioanalytical laboratories who have recognized its exquisite sensitivity, high precision, wide dynamic range, and flexibility in formatting a wide variety of applications. IGEN's M-SERIES™ marks the introduction of the second generation of detection systems employing the ORIGEN technology specifically repackaged to address the needs of the high throughput laboratories involved in drug discovery. Assays are formatted without wash steps. Users realize the high performance of a heterogeneous technology with the convenience of a homogeneous format. The M-SERIES platform can address enzymatic assays (kinases, proteases, helicases, etc.), receptor-ligand or protein-protein assays, immunoassays, quantitation of nucleic acids, as well as other applications. Recent assay formats will be explored in detail.


Author(s):  
Sangsoo Park, Hojun Yeom

A biosignal is used as a control signal for electrical stimulation to restore weakened muscle function due to damage to the central nervous system. In patients with central nervous system damage, sufficient muscle contraction does not occur spontaneously. In this case, applying electrical stimulation can cause normal muscle contraction. However, it is necessary to remove the electrical stimulation artifact caused by the electrical stimulation. This paper describes a system design that removes electrical stimulation artifact in real time using a Cortex-M4-based STM32F processor. The STM32F is a very advantageous MCU for such DSPs, especially because it has a built-in floating point operator. Using STM32F's various high-performance peripherals (12-bit parallel ADC and 12-bit DAC, UART, Timer), an optimized embedded system was implemented.In this paper, the simulated and real-time results were compared and evaluated with the designed fir filter. In addition, the performance of the filter was evaluated through frequency analysis. As a result, it was verified that a high-performance 32-bit STM32F with floating point calculator and various peripherals is suitable for real-time signal processing


2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.


2021 ◽  
Vol MA2021-01 (11) ◽  
pp. 585-585
Author(s):  
Wei Sun ◽  
Mengyu Zhao ◽  
Yahong Chen ◽  
Zhi Zhu ◽  
Ming Zheng

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