Quasihydrostatic versus nonhydrostatic pressure effects on the electrical properties of NiPS3

2021 ◽  
Vol 5 (12) ◽  
Author(s):  
Hengbo Cui ◽  
Seohee Yun ◽  
Kyeong Jun Lee ◽  
Chanhyeon Lee ◽  
Seo Hyoung Chang ◽  
...  
2011 ◽  
Vol 59 (3) ◽  
pp. 506-517 ◽  
Author(s):  
Tongcheng Han ◽  
Angus I. Best ◽  
Jeremy Sothcott ◽  
Lucy M. MacGregor

2020 ◽  
Vol 59 (24) ◽  
pp. 18325-18337
Author(s):  
Enrico Bandiello ◽  
Catalin Popescu ◽  
Estelina Lora da Silva ◽  
Juan Ángel Sans ◽  
Daniel Errandonea ◽  
...  

2006 ◽  
Vol 26 (2-3) ◽  
pp. 177-180 ◽  
Author(s):  
M. Zaghdoudi ◽  
M.M. Abdelkrim ◽  
M. Fathallah ◽  
T. Mohammed-Brahim ◽  
R. Rogel

1967 ◽  
Vol 114 (8) ◽  
pp. 805 ◽  
Author(s):  
Terrell N. Andersen ◽  
Onnig H. Bezirjian ◽  
Henry Eyring

2016 ◽  
Vol 26 (1) ◽  
pp. 27-34
Author(s):  
Nobuyuki KURITA ◽  
Motoi KIMATA ◽  
Hiroyuki SUZUKI ◽  
Takehiko MATSUMOTO ◽  
Keizo MURATA ◽  
...  

Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.


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