An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity

Boltzmann Machine ◽

On Chip

Advances in Intelligent Systems and Computing - Innovations in Bio-Inspired Computing and Applications ◽

Restricted Boltzmann Machine Based Energy Efficient Cognitive Network

10.1007/978-3-319-28031-8_40 ◽

2015 ◽

pp. 463-472 ◽

Cited By ~ 4

Author(s):

P. MohanaPriya ◽

S. Mercy Shalinie ◽

Tulika Pandey

Keyword(s):

Energy Efficient ◽

Boltzmann Machine ◽

Cognitive Network

GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian Inference

IEEE Transactions on Neural Networks and Learning Systems ◽

10.1109/tnnls.2019.2899386 ◽

2020 ◽

Vol 31 (1) ◽

pp. 53-65 ◽

Cited By ~ 1

Author(s):

Wooseok Yi ◽

Junki Park ◽

Jae-Joon Kim

Keyword(s):

Bayesian Inference ◽

Semisupervised Learning ◽

Boltzmann Machine ◽

On Chip

Generative Acoustic-Phonemic-Speaker Model Based on Three-Way Restricted Boltzmann Machine

10.21437/interspeech.2016-1105 ◽

2016 ◽

Cited By ~ 1

Author(s):

Toru Nakashika ◽

Yasuhiro Minami

Keyword(s):

Boltzmann Machine ◽

Model Based

Proceedings of the 26th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining ◽

A Novel Deep Learning Model by Stacking Conditional Restricted Boltzmann Machine and Deep Neural Network

10.1145/3394486.3403184 ◽

2020 ◽

Author(s):

Tianyu Kang ◽

Ping Chen ◽

John Quackenbush ◽

Wei Ding

Keyword(s):

Neural Network ◽

Deep Learning ◽

Deep Neural Network ◽

Learning Model ◽

Boltzmann Machine ◽

Deep Learning Model

A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401530 ◽

2021 ◽

Author(s):

Janak Sharda ◽

Ritvik Sharma ◽

Debanjan Bhowmik

Keyword(s):

Energy Efficient ◽

Crossbar Array ◽

Volatile Memory ◽

On Chip

On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2016.7428045 ◽

2016 ◽

Author(s):

A.K.M. Mahfuzul Islam ◽

Hidetoshi Onodera

Keyword(s):

Energy Efficient ◽

Compensation Scheme ◽

Fine Grain ◽

Body Biasing ◽

On Chip

Learning Invariant Features Using Subspace Restricted Boltzmann Machine

Neural Processing Letters ◽

10.1007/s11063-016-9519-9 ◽

2016 ◽

Vol 45 (1) ◽

pp. 173-182 ◽

Cited By ~ 7

Author(s):

Jakub M. Tomczak ◽

Adam Gonczarek

Keyword(s):

Boltzmann Machine ◽

Invariant Features

Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error

IEICE Transactions on Electronics ◽

10.1587/transele.e100.c.1118 ◽

2017 ◽

Vol E100.C (12) ◽

pp. 1118-1121 ◽

Author(s):

Yasushi FUKUDA ◽

Zule XU ◽

Takayuki KAWAHARA

Keyword(s):

Boltzmann Machine

Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures

2010 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2010.60 ◽

2010 ◽

Author(s):

Iasonas Filippopoulos ◽

Iraklis Anagnostopoulos ◽

Alexandros Bartzas ◽

Dimitrios Soudris ◽

George Economakos

Keyword(s):

Energy Efficient ◽

Network On Chip ◽

Systematic Exploration ◽

On Chip ◽

Application Specific

Energy-efficient optical broadcast for nanophotonic networks-on-chip

2012 Optical Interconnects Conference ◽

10.1109/oic.2012.6224445 ◽

2012 ◽

Author(s):

Cheng Li ◽

Mark Browning ◽

Paul V. Gratz ◽

Samuel Palermo

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

On Chip